1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
|
// Copyright 2021 yuzu Emulator Project
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/bit_field.h"
#include "common/common_types.h"
#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
namespace Shader::Maxwell {
namespace {
void SHR(TranslatorVisitor& v, u64 insn, const IR::U32& shift) {
union {
u64 insn;
BitField<0, 8, IR::Reg> dest_reg;
BitField<8, 8, IR::Reg> src_reg_a;
BitField<39, 1, u64> is_wrapped;
BitField<40, 1, u64> brev;
BitField<43, 1, u64> xmode;
BitField<48, 1, u64> is_arithmetic;
} const shr{insn};
if (shr.xmode != 0) {
throw NotImplementedException("SHR.XMODE");
}
IR::U32 base{v.X(shr.src_reg_a)};
if (shr.brev == 1) {
base = v.ir.BitReverse(base);
}
IR::U32 result;
const IR::U32 safe_shift = shr.is_wrapped == 0 ? shift : v.ir.BitwiseAnd(shift, v.ir.Imm32(31));
if (shr.is_arithmetic == 1) {
result = IR::U32{v.ir.ShiftRightArithmetic(base, safe_shift)};
} else {
result = IR::U32{v.ir.ShiftRightLogical(base, safe_shift)};
}
if (shr.is_wrapped == 0) {
const IR::U32 zero{v.ir.Imm32(0)};
const IR::U32 safe_bits{v.ir.Imm32(32)};
const IR::U1 is_negative{v.ir.ILessThan(result, zero, true)};
const IR::U1 is_safe{v.ir.ILessThan(shift, safe_bits, false)};
const IR::U32 clamped_value{v.ir.Select(is_negative, v.ir.Imm32(-1), zero)};
result = IR::U32{v.ir.Select(is_safe, result, clamped_value)};
}
v.X(shr.dest_reg, result);
}
} // Anonymous namespace
void TranslatorVisitor::SHR_reg(u64 insn) {
SHR(*this, insn, GetReg20(insn));
}
void TranslatorVisitor::SHR_cbuf(u64 insn) {
SHR(*this, insn, GetCbuf(insn));
}
void TranslatorVisitor::SHR_imm(u64 insn) {
SHR(*this, insn, GetImm20(insn));
}
} // namespace Shader::Maxwell
|
