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2023-12-26core: track separate heap allocation for linuxLiam1-0/+20
2023-06-13core: decouple ARM interface from DynarmicLiam1-0/+29
2020-03-03core: Implement separate A32/A64 ARM interfaces.bunnei1-96/+0
2020-02-26ARM_Interface: Cache the JITs instead of deleting/recreating.Fernando Sahmkow1-2/+10
2019-11-27core/memory: Migrate over Write{8, 16, 32, 64, Block} to the Memory classLioncash1-1/+6
2019-11-27core: Prepare various classes for memory read/write migrationLioncash1-1/+0
2019-07-11core/arm: Remove obsolete Unicorn memory mappingLioncash1-3/+0
2019-04-12core/cpu_core_manager: Create threads separately from initialization.Lioncash1-2/+4
2019-04-08kernel/svc: Deglobalize the supervisor call handlersLioncash1-7/+3
2019-04-07arm/arm_dynarmic: Remove unnecessary current_page_table memberLioncash1-6/+0
2019-04-04core: Add missing override specifiers where applicableLioncash1-2/+2
2019-03-17core: Move PageTable struct into Common.bunnei1-2/+2
2019-02-16core_timing: Convert core timing into a classLioncash1-1/+7
2018-12-19Moved backtrace to ArmInterfaceDavid Marcec1-2/+0
2018-12-03Moved backtrace to ArmInterfaceDavid Marcec1-0/+2
2018-10-15core: Make the exclusive monitor a unique_ptr instead of a shared_ptrLioncash1-2/+2
2018-09-21arm_interface: Replace kernel vm_manager include with a forward declarationLioncash1-0/+4
2018-09-18arm_interface: Remove ARM11-isms from the CPU interfaceLioncash1-6/+4
2018-09-15Port #4182 from Citra: "Prefix all size_t with std::"fearlessTobi1-11/+11
2018-08-25core: Namespace all code in the arm subdirectory under the Core namespaceLioncash1-0/+4
2018-07-24arm_dynarmic: Make MakeJit() a const member functionLioncash1-1/+1
2018-07-24exclusive_monitor: Use consistent type alias for u64Lioncash1-7/+6
2018-07-22Implement exclusive monitorMerryMage1-1/+29
2018-07-21CPU: Save and restore the TPIDR_EL0 system register on every context switch.Subv1-0/+2
2018-07-16scheduler: Clear exclusive state when switching contextsMerryMage1-0/+1
2018-03-16arm_interface: Support unmapping previously mapped memory.bunnei1-1/+1
2018-02-25Implements citra-emu/citra#3184N00byKing1-1/+4
2018-02-09dynarmic: Update to 41ae12263MerryMage1-1/+1
2018-01-13yuzu: Update license text to be consistent across project.bunnei1-1/+1
2018-01-12arm_dynarmic: Implement coreMerryMage1-2/+14
2018-01-04arm_dynarmic: More cleanup.bunnei1-6/+0
2018-01-04arm_dynarmic: Gut interface until dynarmic is ready for general use.bunnei1-8/+3
2018-01-03arm: Remove SkyEye/Dyncom code that is ARMv6-only.bunnei1-6/+1
2017-09-30arm_interface: Set TLS address for dynarmic core.bunnei1-0/+2
2017-09-30arm: Use 64-bit addressing in a bunch of places.bunnei1-4/+4
2017-09-30Moved down_count to CoreTimingHuw Pascoe1-2/+0
2017-09-25ARM_Interface: Implement PageTableChangedMerryMage1-1/+9
2017-02-03arm_dynarmic: CP15 supportMerryMage1-1/+1
2016-12-22ThreadContext: Move from "core" to "arm_interface".bunnei1-6/+2
2016-09-21Remove empty newlines in #include blocks.Emmanuel Gil Peyrot1-3/+0
2016-09-15arm: ResetContext shouldn't be part of ARM_Interface.bunnei1-1/+0
2016-09-15arm_dynarmic/arm_dyncom: Remove unnecessary "virtual" keyword.bunnei1-1/+1
2016-09-15dynarmic: Implement ARM CPU interface.bunnei1-8/+9
2016-08-27ARM: add ClearInstructionCache functionwwylele1-0/+2
2015-08-07arm_interface: Implement interface for retrieving VFP registersLioncash1-0/+4
2015-07-26dyncom: Rename armdefs.h to armstate.hLioncash1-1/+1
2015-06-28Core: Cleanup core includes.Emmanuel Gil Peyrot1-0/+5
2015-05-11fixup! Set the TLS address in the schedulerSubv1-1/+1
2015-05-11Core/Memory: Give every emulated thread it's own TLS area.Subv1-1/+1
2015-04-14Headers: Add some forgotten overrides, thanks clang!Emmanuel Gil Peyrot1-1/+1
2015-04-06arm_interface: Support retrieval/storage to CP15 registersLioncash1-0/+2
2015-03-16arm_interface: Get rid of GetTicks.Lioncash1-1/+0
2015-02-13dyncom: Switch the app and system cores into the correct mode at initializationLioncash1-1/+1
2015-02-10Scheduler refactor Pt. 1Kevin Hartman1-56/+1
2015-01-09Move ThreadContext to core/core.h and deal with the falloutYuri Kunde Schlesner1-2/+2
2015-01-09Timing: Use CoreTiming::GetTicks to keep track of ticks.Subv1-3/+0
2014-12-26ARM: Add a mechanism for faking CPU time elapsed during HLE.bunnei1-4/+10
2014-12-21License changepurpasmart961-1/+1
2014-11-19Remove trailing spaces in every file but the ones imported from SkyEye, AOSP or generatedEmmanuel Gil Peyrot1-1/+1
2014-11-18Fix documentation of parametersLioncash1-1/+1
2014-10-26Add `override` keyword through the code.Yuri Kunde Schlesner1-7/+7
2014-10-25ARM: Integrate SkyEye faster "dyncom" interpreter.bunnei1-8/+8
2014-10-25ARM: Reorganized file structure to move shared SkyEye code to a more common area.bunnei1-2/+2
2014-06-02arm: added option to prepare CPU core (while mid-instruction) for thread reschedulebunnei1-0/+3
2014-05-21ARM_Interpreter/ARM_Interface: Fixed member variable naming to be consistent with style guidebunnei1-1/+1
2014-05-21ARM_Interface: added SaveContext and LoadContext functions for HLE thread switchingbunnei1-0/+12
2014-05-17updated how we call ARM core to make things much fasterbunnei1-2/+5
2014-05-12added option to set CPSR register to arm_interfacebunnei1-0/+6
2014-04-28removed DISALLOW_COPY_AND_ASSIGN in favor of NonCopyable classbunnei1-1/+0
2014-04-11cleaned up arm_interface, added a setter to set registers for use with HLE return valuesbunnei1-2/+35
2014-04-09fixed licensing and updated code style naming for arm_interface/arm_interpreter frontend modulebunnei1-30/+8
2014-04-09fixed project includes to use new directory structurebunnei1-5/+4
2014-04-09got rid of 'src' folders in each sub-projectbunnei1-0/+0
2014-04-05changed hw_lcd to use ARM core correct tick counter instead of [what was actually] just an instruction count. this seems to fix timing issues with the 3DS_Homebrew_Pong3Dv2 demo.bunnei1-0/+7
2014-04-05- added an interface layer for ARM coresbunnei1-28/+21
2013-10-06fixed a typo in declaration of meta file systemShizZy1-2/+2
2013-10-03moved some core functions over to system moduleShizZy1-1/+6
2013-10-02added core_timing and system modules to core vcprojShizZy1-0/+52
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