12 files changed, 101 insertions, 53 deletions

diff --git a/src/video_core/CMakeLists.txt b/src/video_core/CMakeLists.txt
index 70728d2f6..ed87f8ff1 100644
--- a/src/video_core/CMakeLists.txt
+++ b/src/video_core/CMakeLists.txt
@@ -7,6 +7,9 @@ add_library(video_core STATIC
     engines/maxwell_3d.h
     engines/maxwell_compute.cpp
     engines/maxwell_compute.h
+    gpu.h
+    memory_manager.cpp
+    memory_manager.h
     renderer_base.cpp
     renderer_base.h
     renderer_opengl/gl_resource_manager.h
diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp
index e1df875e7..21d672085 100644
--- a/src/video_core/command_processor.cpp
+++ b/src/video_core/command_processor.cpp
@@ -16,30 +16,18 @@
 #include "video_core/engines/fermi_2d.h"
 #include "video_core/engines/maxwell_3d.h"
 #include "video_core/engines/maxwell_compute.h"
+#include "video_core/gpu.h"
 #include "video_core/renderer_base.h"
 #include "video_core/video_core.h"
 
 namespace Tegra {
 
-namespace CommandProcessor {
-
 enum class BufferMethods {
     BindObject = 0,
     CountBufferMethods = 0x100,
 };
 
-enum class EngineID {
-    FERMI_TWOD_A = 0x902D, // 2D Engine
-    MAXWELL_B = 0xB197,    // 3D Engine
-    MAXWELL_COMPUTE_B = 0xB1C0,
-    KEPLER_INLINE_TO_MEMORY_B = 0xA140,
-    MAXWELL_DMA_COPY_A = 0xB0B5,
-};
-
-// Mapping of subchannels to their bound engine ids.
-static std::unordered_map<u32, EngineID> bound_engines;
-
-static void WriteReg(u32 method, u32 subchannel, u32 value) {
+void GPU::WriteReg(u32 method, u32 subchannel, u32 value) {
     LOG_WARNING(HW_GPU, "Processing method %08X on subchannel %u value %08X", method, subchannel,
                 value);
 
@@ -63,22 +51,25 @@ static void WriteReg(u32 method, u32 subchannel, u32 value) {
 
     switch (engine) {
     case EngineID::FERMI_TWOD_A:
-        Engines::Fermi2D::WriteReg(method, value);
+        fermi_2d->WriteReg(method, value);
         break;
     case EngineID::MAXWELL_B:
-        Engines::Maxwell3D::WriteReg(method, value);
+        maxwell_3d->WriteReg(method, value);
         break;
     case EngineID::MAXWELL_COMPUTE_B:
-        Engines::MaxwellCompute::WriteReg(method, value);
+        maxwell_compute->WriteReg(method, value);
         break;
     default:
         UNIMPLEMENTED();
     }
 }
 
-void ProcessCommandList(VAddr address, u32 size) {
-    VAddr current_addr = address;
-    while (current_addr < address + size * sizeof(CommandHeader)) {
+void GPU::ProcessCommandList(GPUVAddr address, u32 size) {
+    // TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an
+    // application VAddr.
+    const VAddr head_address = memory_manager->PhysicalToVirtualAddress(address);
+    VAddr current_addr = head_address;
+    while (current_addr < head_address + size * sizeof(CommandHeader)) {
         const CommandHeader header = {Memory::Read32(current_addr)};
         current_addr += sizeof(u32);
 
@@ -125,6 +116,4 @@ void ProcessCommandList(VAddr address, u32 size) {
     }
 }
 
-} // namespace CommandProcessor
-
 } // namespace Tegra
diff --git a/src/video_core/command_processor.h b/src/video_core/command_processor.h
index 90e64629e..b511bfcf7 100644
--- a/src/video_core/command_processor.h
+++ b/src/video_core/command_processor.h
@@ -10,8 +10,6 @@
 
 namespace Tegra {
 
-namespace CommandProcessor {
-
 enum class SubmissionMode : u32 {
     IncreasingOld = 0,
     Increasing = 1,
@@ -38,6 +36,4 @@ static_assert(sizeof(CommandHeader) == sizeof(u32), "CommandHeader has incorrect
 
 void ProcessCommandList(VAddr address, u32 size);
 
-} // namespace CommandProcessor
-
 } // namespace Tegra
diff --git a/src/video_core/engines/fermi_2d.cpp b/src/video_core/engines/fermi_2d.cpp
index 3d62c321f..7aab163dc 100644
--- a/src/video_core/engines/fermi_2d.cpp
+++ b/src/video_core/engines/fermi_2d.cpp
@@ -6,10 +6,8 @@
 
 namespace Tegra {
 namespace Engines {
-namespace Fermi2D {
 
-void WriteReg(u32 method, u32 value) {}
+void Fermi2D::WriteReg(u32 method, u32 value) {}
 
-} // namespace Fermi2D
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h
index 6f3f5dfbc..8967ddede 100644
--- a/src/video_core/engines/fermi_2d.h
+++ b/src/video_core/engines/fermi_2d.h
@@ -8,11 +8,15 @@
 
 namespace Tegra {
 namespace Engines {
-namespace Fermi2D {
 
-void WriteReg(u32 method, u32 value);
+class Fermi2D final {
+public:
+    Fermi2D() = default;
+    ~Fermi2D() = default;
 
-} // namespace Fermi2D
+    /// Write the value to the register identified by method.
+    void WriteReg(u32 method, u32 value);
+};
 
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index c2697c960..ccdb310f0 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -6,10 +6,8 @@
 
 namespace Tegra {
 namespace Engines {
-namespace Maxwell3D {
 
-void WriteReg(u32 method, u32 value) {}
+void Maxwell3D::WriteReg(u32 method, u32 value) {}
 
-} // namespace Maxwell3D
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 6957fb721..0f4ae1328 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -8,11 +8,15 @@
 
 namespace Tegra {
 namespace Engines {
-namespace Maxwell3D {
 
-void WriteReg(u32 method, u32 value);
+class Maxwell3D final {
+public:
+    Maxwell3D() = default;
+    ~Maxwell3D() = default;
 
-} // namespace Maxwell3D
+    /// Write the value to the register identified by method.
+    void WriteReg(u32 method, u32 value);
+};
 
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp
index c2134d63b..e4e5f9e5e 100644
--- a/src/video_core/engines/maxwell_compute.cpp
+++ b/src/video_core/engines/maxwell_compute.cpp
@@ -6,10 +6,8 @@
 
 namespace Tegra {
 namespace Engines {
-namespace MaxwellCompute {
 
-void WriteReg(u32 method, u32 value) {}
+void MaxwellCompute::WriteReg(u32 method, u32 value) {}
 
-} // namespace MaxwellCompute
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/engines/maxwell_compute.h b/src/video_core/engines/maxwell_compute.h
index dc9a13593..7262e1bcb 100644
--- a/src/video_core/engines/maxwell_compute.h
+++ b/src/video_core/engines/maxwell_compute.h
@@ -8,11 +8,15 @@
 
 namespace Tegra {
 namespace Engines {
-namespace MaxwellCompute {
 
-void WriteReg(u32 method, u32 value);
+class MaxwellCompute final {
+public:
+    MaxwellCompute() = default;
+    ~MaxwellCompute() = default;
 
-} // namespace MaxwellCompute
+    /// Write the value to the register identified by method.
+    void WriteReg(u32 method, u32 value);
+};
 
 } // namespace Engines
 } // namespace Tegra
diff --git a/src/video_core/gpu.h b/src/video_core/gpu.h
new file mode 100644
index 000000000..a961f3fd4
--- /dev/null
+++ b/src/video_core/gpu.h
@@ -0,0 +1,55 @@
+// Copyright 2018 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include <memory>
+#include <unordered_map>
+#include "common/common_types.h"
+#include "video_core/engines/fermi_2d.h"
+#include "video_core/engines/maxwell_3d.h"
+#include "video_core/engines/maxwell_compute.h"
+#include "video_core/memory_manager.h"
+
+namespace Tegra {
+
+enum class EngineID {
+    FERMI_TWOD_A = 0x902D, // 2D Engine
+    MAXWELL_B = 0xB197,    // 3D Engine
+    MAXWELL_COMPUTE_B = 0xB1C0,
+    KEPLER_INLINE_TO_MEMORY_B = 0xA140,
+    MAXWELL_DMA_COPY_A = 0xB0B5,
+};
+
+class GPU final {
+public:
+    GPU() {
+        memory_manager = std::make_unique<MemoryManager>();
+        maxwell_3d = std::make_unique<Engines::Maxwell3D>();
+        fermi_2d = std::make_unique<Engines::Fermi2D>();
+        maxwell_compute = std::make_unique<Engines::MaxwellCompute>();
+    }
+    ~GPU() = default;
+
+    /// Processes a command list stored at the specified address in GPU memory.
+    void ProcessCommandList(GPUVAddr address, u32 size);
+
+    std::unique_ptr<MemoryManager> memory_manager;
+
+private:
+    /// Writes a single register in the engine bound to the specified subchannel
+    void WriteReg(u32 method, u32 subchannel, u32 value);
+
+    /// Mapping of command subchannels to their bound engine ids.
+    std::unordered_map<u32, EngineID> bound_engines;
+
+    /// 3D engine
+    std::unique_ptr<Engines::Maxwell3D> maxwell_3d;
+    /// 2D engine
+    std::unique_ptr<Engines::Fermi2D> fermi_2d;
+    /// Compute engine
+    std::unique_ptr<Engines::MaxwellCompute> maxwell_compute;
+};
+
+} // namespace Tegra
diff --git a/src/core/hle/service/nvdrv/memory_manager.cpp b/src/video_core/memory_manager.cpp
index 55a8675d5..2789a4ca1 100644
--- a/src/core/hle/service/nvdrv/memory_manager.cpp
+++ b/src/video_core/memory_manager.cpp
@@ -3,10 +3,9 @@
 // Refer to the license.txt file included.
 
 #include "common/assert.h"
-#include "core/hle/service/nvdrv/memory_manager.h"
+#include "video_core/memory_manager.h"
 
-namespace Service {
-namespace Nvidia {
+namespace Tegra {
 
 PAddr MemoryManager::AllocateSpace(u64 size, u64 align) {
     boost::optional<PAddr> paddr = FindFreeBlock(size, align);
@@ -108,5 +107,4 @@ VAddr& MemoryManager::PageSlot(PAddr paddr) {
     return (*block)[(paddr >> Memory::PAGE_BITS) & PAGE_BLOCK_MASK];
 }
 
-} // namespace Nvidia
-} // namespace Service
+} // namespace Tegra
diff --git a/src/core/hle/service/nvdrv/memory_manager.h b/src/video_core/memory_manager.h
index 4ba1a3952..47da7acd6 100644
--- a/src/core/hle/service/nvdrv/memory_manager.h
+++ b/src/video_core/memory_manager.h
@@ -9,8 +9,10 @@
 #include "common/common_types.h"
 #include "core/memory.h"
 
-namespace Service {
-namespace Nvidia {
+namespace Tegra {
+
+/// Virtual addresses in the GPU's memory map are 64 bit.
+using GPUVAddr = u64;
 
 class MemoryManager final {
 public:
@@ -44,5 +46,4 @@ private:
     std::array<std::unique_ptr<PageBlock>, PAGE_TABLE_SIZE> page_table{};
 };
 
-} // namespace Nvidia
-} // namespace Service
+} // namespace Tegra