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-rw-r--r--src/core/arm/skyeye_common/armmmu.h99
1 files changed, 9 insertions, 90 deletions
diff --git a/src/core/arm/skyeye_common/armmmu.h b/src/core/arm/skyeye_common/armmmu.h
index 30858f9ba..6e54142ee 100644
--- a/src/core/arm/skyeye_common/armmmu.h
+++ b/src/core/arm/skyeye_common/armmmu.h
@@ -18,19 +18,10 @@
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
-#ifndef _ARMMMU_H_
-#define _ARMMMU_H_
+#pragma once
-
-#define WORD_SHT 2
-#define WORD_SIZE (1<<WORD_SHT)
-/* The MMU is accessible with MCR and MRC operations to copro 15: */
-
-#define MMU_COPRO (15)
-
-/* Register numbers in the MMU: */
-
-typedef enum mmu_regnum_t
+// Register numbers in the MMU
+enum
{
MMU_ID = 0,
MMU_CONTROL = 1,
@@ -44,94 +35,22 @@ typedef enum mmu_regnum_t
MMU_TLB_LOCKDOWN = 10,
MMU_PID = 13,
- /*MMU_V4 */
+ // MMU_V4
MMU_V4_CACHE_OPS = 7,
MMU_V4_TLB_OPS = 8,
- /*MMU_V3 */
+ // MMU_V3
MMU_V3_FLUSH_TLB = 5,
MMU_V3_FLUSH_TLB_ENTRY = 6,
MMU_V3_FLUSH_CACHE = 7,
- /*MMU Intel SA-1100 */
+ // MMU Intel SA-1100
MMU_SA_RB_OPS = 9,
MMU_SA_DEBUG = 14,
MMU_SA_CP15_R15 = 15,
- //chy 2003-08-24
- /*Intel xscale CP15 */
+
+ // Intel xscale CP15
XSCALE_CP15_CACHE_TYPE = 0,
XSCALE_CP15_AUX_CONTROL = 1,
XSCALE_CP15_COPRO_ACCESS = 15,
-
-} mmu_regnum_t;
-
-/* Bits in the control register */
-
-#define CONTROL_MMU (1<<0)
-#define CONTROL_ALIGN_FAULT (1<<1)
-#define CONTROL_CACHE (1<<2)
-#define CONTROL_DATA_CACHE (1<<2)
-#define CONTROL_WRITE_BUFFER (1<<3)
-#define CONTROL_BIG_ENDIAN (1<<7)
-#define CONTROL_SYSTEM (1<<8)
-#define CONTROL_ROM (1<<9)
-#define CONTROL_UNDEFINED (1<<10)
-#define CONTROL_BRANCH_PREDICT (1<<11)
-#define CONTROL_INSTRUCTION_CACHE (1<<12)
-#define CONTROL_VECTOR (1<<13)
-#define CONTROL_RR (1<<14)
-#define CONTROL_L4 (1<<15)
-#define CONTROL_XP (1<<23)
-#define CONTROL_EE (1<<25)
-
-/*Macro defines for MMU state*/
-#define MMU_CTL (state->mmu.control)
-#define MMU_Enabled (state->mmu.control & CONTROL_MMU)
-#define MMU_Disabled (!(MMU_Enabled))
-#define MMU_Aligned (state->mmu.control & CONTROL_ALIGN_FAULT)
-
-#define MMU_ICacheEnabled (MMU_CTL & CONTROL_INSTRUCTION_CACHE)
-#define MMU_ICacheDisabled (!(MMU_ICacheDisabled))
-
-#define MMU_DCacheEnabled (MMU_CTL & CONTROL_DATA_CACHE)
-#define MMU_DCacheDisabled (!(MMU_DCacheEnabled))
-
-#define MMU_CacheEnabled (MMU_CTL & CONTROL_CACHE)
-#define MMU_CacheDisabled (!(MMU_CacheEnabled))
-
-#define MMU_WBEnabled (MMU_CTL & CONTROL_WRITE_BUFFER)
-#define MMU_WBDisabled (!(MMU_WBEnabled))
-
-/*virt_addr exchange according to CP15.R13(process id virtul mapping)*/
-#define PID_VA_MAP_MASK 0xfe000000
-//#define mmu_pid_va_map(va) ({\
-// ARMword ret; \
-// if ((va) & PID_VA_MAP_MASK)\
-// ret = (va); \
-// else \
-// ret = ((va) | (state->mmu.process_id & PID_VA_MAP_MASK));\
-// ret;\
-//})
-#define mmu_pid_va_map(va) ((va) & PID_VA_MAP_MASK) ? (va) : ((va) | (state->mmu.process_id & PID_VA_MAP_MASK))
-
-/* FS[3:0] in the fault status register: */
-
-typedef enum fault_t
-{
- NO_FAULT = 0x0,
- ALIGNMENT_FAULT = 0x1,
-
- SECTION_TRANSLATION_FAULT = 0x5,
- PAGE_TRANSLATION_FAULT = 0x7,
- SECTION_DOMAIN_FAULT = 0x9,
- PAGE_DOMAIN_FAULT = 0xB,
- SECTION_PERMISSION_FAULT = 0xD,
- SUBPAGE_PERMISSION_FAULT = 0xF,
-
- /* defined by skyeye */
- TLB_READ_MISS = 0x30,
- TLB_WRITE_MISS = 0x40,
-
-} fault_t;
-
-#endif /* _ARMMMU_H_ */
+};