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authorbunnei <ericbunnie@gmail.com>2014-04-12 07:36:39 +0200
committerbunnei <ericbunnie@gmail.com>2014-04-12 07:36:39 +0200
commit4d8831890321c11e2e29ed9bc87c8a48841b702e (patch)
treeea8dd68bf261e34c49593d0bd812adc91c084799 /src
parentadded a SETABORT method that does not update LR (for HLE'd SVC that does not jump appcore CPU to an IRQ vector) (diff)
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Diffstat (limited to 'src')
-rw-r--r--src/core/arm/interpreter/arminit.cpp8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp
index cdbd02f3c..a8aeecdea 100644
--- a/src/core/arm/interpreter/arminit.cpp
+++ b/src/core/arm/interpreter/arminit.cpp
@@ -530,9 +530,13 @@ ARMul_Abort (ARMul_State * state, ARMword vector)
isize);
break;
case ARMul_SWIV: /* Software Interrupt */
- SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE,
+ // Modified SETABORT that doesn't branch to a SVC vector as we are implementing this in HLE
+ // Instead of doing normal routine, backup R15 by one instruction (this is what PC will get
+ // set to, making it the next instruction after the SVC call), and skip setting the LR.
+ SETABORT_SKIPBRANCH (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE,
isize);
- break;
+ state->Reg[15] -= 4;
+ return;
case ARMul_PrefetchAbortV: /* Prefetch Abort */
state->AbortAddr = 1;
SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE,