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authorbunnei <bunneidev@gmail.com>2015-01-19 22:42:31 +0100
committerbunnei <bunneidev@gmail.com>2015-01-19 22:42:31 +0100
commit004b23153b2864f6072f0c71027f392b6b424510 (patch)
tree5d0c320ed65b23b3661f6a4a7144f02da49e78cd /src
parentMerge pull request #383 from zhuowei/shared_page (diff)
parentdyncom: Implement missing shifts in ScaledRegisterPostIndexed, etc (diff)
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Diffstat (limited to 'src')
-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp40
1 files changed, 33 insertions, 7 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index d0347566c..ffe9d17f9 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -410,10 +410,21 @@ void LnSWoUB(ScaledRegisterPreIndexed)(arm_processor *cpu, unsigned int inst, un
}
break;
case 2:
- DEBUG_MSG;
+ if (shift_imm == 0) { // ASR #32
+ if (BIT(rm, 31) == 1)
+ index = 0xFFFFFFFF;
+ else
+ index = 0;
+ } else {
+ index = static_cast<int>(rm) >> shift_imm;
+ }
break;
case 3:
- DEBUG_MSG;
+ if (shift_imm == 0) {
+ index = (cpu->CFlag << 31) | (rm >> 1);
+ } else {
+ index = ROTATE_RIGHT_32(rm, shift_imm);
+ }
break;
}
@@ -449,10 +460,21 @@ void LnSWoUB(ScaledRegisterPostIndexed)(arm_processor *cpu, unsigned int inst, u
}
break;
case 2:
- DEBUG_MSG;
+ if (shift_imm == 0) { // ASR #32
+ if (BIT(rm, 31) == 1)
+ index = 0xFFFFFFFF;
+ else
+ index = 0;
+ } else {
+ index = static_cast<int>(rm) >> shift_imm;
+ }
break;
case 3:
- DEBUG_MSG;
+ if (shift_imm == 0) {
+ index = (cpu->CFlag << 31) | (rm >> 1);
+ } else {
+ index = ROTATE_RIGHT_32(rm, shift_imm);
+ }
break;
}
@@ -654,8 +676,8 @@ void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsign
}
break;
case 2:
- if (shift_imm == 0){ // ASR #32
- if (rm >> 31)
+ if (shift_imm == 0) { // ASR #32
+ if (BIT(rm, 31) == 1)
index = 0xFFFFFFFF;
else
index = 0;
@@ -664,7 +686,11 @@ void LnSWoUB(ScaledRegisterOffset)(arm_processor *cpu, unsigned int inst, unsign
}
break;
case 3:
- DEBUG_MSG;
+ if (shift_imm == 0) {
+ index = (cpu->CFlag << 31) | (rm >> 1);
+ } else {
+ index = ROTATE_RIGHT_32(rm, shift_imm);
+ }
break;
}