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authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-21 04:05:42 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:50 +0100
commite3f1233ce13d82623173d690a6aa7819d68f069e (patch)
treeb2c02448aede72d7482c16c20f77e1e9e7864a42 /src/video_core/shader/decode
parentshader_decode: Implement FADD32I (diff)
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Diffstat (limited to 'src/video_core/shader/decode')
-rw-r--r--src/video_core/shader/decode/memory.cpp40
1 files changed, 39 insertions, 1 deletions
diff --git a/src/video_core/shader/decode/memory.cpp b/src/video_core/shader/decode/memory.cpp
index d6086004b..30e2b33a3 100644
--- a/src/video_core/shader/decode/memory.cpp
+++ b/src/video_core/shader/decode/memory.cpp
@@ -9,14 +9,52 @@
namespace VideoCommon::Shader {
+using Tegra::Shader::Attribute;
using Tegra::Shader::Instruction;
using Tegra::Shader::OpCode;
+using Tegra::Shader::Register;
u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
const Instruction instr = {program_code[pc]};
const auto opcode = OpCode::Decode(instr);
- UNIMPLEMENTED();
+ switch (opcode->get().GetId()) {
+ case OpCode::Id::LD_A: {
+ // Note: Shouldn't this be interp mode flat? As in no interpolation made.
+ UNIMPLEMENTED_IF_MSG(instr.gpr8.Value() != Register::ZeroIndex,
+ "Indirect attribute loads are not supported");
+ UNIMPLEMENTED_IF_MSG((instr.attribute.fmt20.immediate.Value() % sizeof(u32)) != 0,
+ "Unaligned attribute loads are not supported");
+
+ Tegra::Shader::IpaMode input_mode{Tegra::Shader::IpaInterpMode::Perspective,
+ Tegra::Shader::IpaSampleMode::Default};
+
+ u64 next_element = instr.attribute.fmt20.element;
+ auto next_index = static_cast<u64>(instr.attribute.fmt20.index.Value());
+
+ const auto LoadNextElement = [&](u32 reg_offset) {
+ const Node buffer = GetRegister(instr.gpr39);
+ const Node attribute = GetInputAttribute(static_cast<Attribute::Index>(next_index),
+ next_element, input_mode, buffer);
+
+ SetRegister(bb, instr.gpr0.Value() + reg_offset, attribute);
+
+ // Load the next attribute element into the following register. If the element
+ // to load goes beyond the vec4 size, load the first element of the next
+ // attribute.
+ next_element = (next_element + 1) % 4;
+ next_index = next_index + (next_element == 0 ? 1 : 0);
+ };
+
+ const u32 num_words = static_cast<u32>(instr.attribute.fmt20.size.Value()) + 1;
+ for (u32 reg_offset = 0; reg_offset < num_words; ++reg_offset) {
+ LoadNextElement(reg_offset);
+ }
+ break;
+ }
+ default:
+ UNIMPLEMENTED_MSG("Unhandled memory instruction: {}", opcode->get().GetName());
+ }
return pc;
}