summaryrefslogtreecommitdiffstats
path: root/src/video_core/shader/decode
diff options
context:
space:
mode:
authorReinUsesLisp <reinuseslisp@airmail.cc>2018-12-26 05:49:32 +0100
committerReinUsesLisp <reinuseslisp@airmail.cc>2019-01-15 21:54:53 +0100
commitd9118d324a7f40ad9227e15408be528273743bee (patch)
tree045666fb020028bcd98fb7f19d482a39882cd2ea /src/video_core/shader/decode
parentshader_decode: Implement TEXS.F16 (diff)
downloadyuzu-d9118d324a7f40ad9227e15408be528273743bee.tar
yuzu-d9118d324a7f40ad9227e15408be528273743bee.tar.gz
yuzu-d9118d324a7f40ad9227e15408be528273743bee.tar.bz2
yuzu-d9118d324a7f40ad9227e15408be528273743bee.tar.lz
yuzu-d9118d324a7f40ad9227e15408be528273743bee.tar.xz
yuzu-d9118d324a7f40ad9227e15408be528273743bee.tar.zst
yuzu-d9118d324a7f40ad9227e15408be528273743bee.zip
Diffstat (limited to 'src/video_core/shader/decode')
-rw-r--r--src/video_core/shader/decode/memory.cpp17
1 files changed, 11 insertions, 6 deletions
diff --git a/src/video_core/shader/decode/memory.cpp b/src/video_core/shader/decode/memory.cpp
index 679e7f01b..60bdd9b73 100644
--- a/src/video_core/shader/decode/memory.cpp
+++ b/src/video_core/shader/decode/memory.cpp
@@ -91,12 +91,14 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.offset + 4, index);
const Node composite =
- Operation(OperationCode::Composite, op_a, op_b, GetRegister(RZ), GetRegister(RZ));
+ Operation(OperationCode::Composite, op_a, op_b, GetRegister(Register::ZeroIndex),
+ GetRegister(Register::ZeroIndex));
MetaComponents meta{{0, 1, 2, 3}};
bb.push_back(Operation(OperationCode::AssignComposite, meta, composite,
GetRegister(instr.gpr0), GetRegister(instr.gpr0.Value() + 1),
- GetRegister(RZ), GetRegister(RZ)));
+ GetRegister(Register::ZeroIndex),
+ GetRegister(Register::ZeroIndex)));
break;
}
default:
@@ -197,7 +199,8 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
++dest_elem;
}
- std::generate(dest.begin() + dest_elem, dest.end(), [&]() { return GetRegister(RZ); });
+ std::generate(dest.begin() + dest_elem, dest.end(),
+ [&]() { return GetRegister(Register::ZeroIndex); });
bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta), texture, dest[0],
dest[1], dest[2], dest[3]));
@@ -255,7 +258,8 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
++dest_elem;
}
- std::generate(dest.begin() + dest_elem, dest.end(), [&]() { return GetRegister(RZ); });
+ std::generate(dest.begin() + dest_elem, dest.end(),
+ [&]() { return GetRegister(Register::ZeroIndex); });
bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta_components), texture,
dest[0], dest[1], dest[2], dest[3]));
@@ -369,7 +373,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
const MetaComponents meta_composite{{0, 1, 2, 3}};
bb.push_back(Operation(OperationCode::AssignComposite, meta_composite, texture,
GetRegister(instr.gpr0), GetRegister(instr.gpr0.Value() + 1),
- GetRegister(RZ), GetRegister(RZ)));
+ GetRegister(Register::ZeroIndex), GetRegister(Register::ZeroIndex)));
break;
}
case OpCode::Id::TLDS: {
@@ -438,7 +442,8 @@ void ShaderIR::WriteTexsInstructionFloat(BasicBlock& bb, Instruction instr, Node
++meta.count;
}
- std::generate(dest.begin() + meta.count, dest.end(), [&]() { return GetRegister(RZ); });
+ std::generate(dest.begin() + meta.count, dest.end(),
+ [&]() { return GetRegister(Register::ZeroIndex); });
bb.push_back(Operation(OperationCode::AssignComposite, meta, texture, dest[0], dest[1], dest[2],
dest[3]));