2 files changed, 8 insertions, 8 deletions

diff --git a/src/video_core/shader/decode/memory.cpp b/src/video_core/shader/decode/memory.cpp
index 60bdd9b73..f3f78a662 100644
--- a/src/video_core/shader/decode/memory.cpp
+++ b/src/video_core/shader/decode/memory.cpp
@@ -155,8 +155,8 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
         break;
     }
     case OpCode::Id::ST_L: {
-        // UNIMPLEMENTED_IF_MSG(instr.st_l.unknown == 0, "ST_L Unhandled mode: {}",
-        //                      static_cast<u32>(instr.st_l.unknown.Value()));
+        UNIMPLEMENTED_IF_MSG(instr.st_l.unknown == 0, "ST_L Unhandled mode: {}",
+                             static_cast<u32>(instr.st_l.unknown.Value()));
 
         const Node index = Operation(OperationCode::IAdd, NO_PRECISE, GetRegister(instr.gpr8),
                                      Immediate(static_cast<s32>(instr.smem_imm)));
diff --git a/src/video_core/shader/decode/other.cpp b/src/video_core/shader/decode/other.cpp
index 386433d8e..6e6795ba7 100644
--- a/src/video_core/shader/decode/other.cpp
+++ b/src/video_core/shader/decode/other.cpp
@@ -54,7 +54,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
         UNIMPLEMENTED_IF_MSG(cc != Tegra::Shader::ConditionCode::T, "KIL condition code used: {}",
                              static_cast<u32>(cc));
 
-        bb.push_back(Operation(OperationCode::Kil));
+        bb.push_back(Operation(OperationCode::Discard));
         break;
     }
     case OpCode::Id::MOV_SYS: {
@@ -79,7 +79,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
                              "BRA with constant buffers are not implemented");
 
         const u32 target = pc + instr.bra.GetBranchTarget();
-        const Node branch = Operation(OperationCode::Bra, Immediate(target));
+        const Node branch = Operation(OperationCode::Branch, Immediate(target));
 
         const Tegra::Shader::ConditionCode cc = instr.flow_condition_code;
         if (cc != Tegra::Shader::ConditionCode::T) {
@@ -97,7 +97,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
         // target of the jump that the SYNC instruction will make. The SSY opcode has a similar
         // structure to the BRA opcode.
         const u32 target = pc + instr.bra.GetBranchTarget();
-        bb.push_back(Operation(OperationCode::Ssy, Immediate(target)));
+        bb.push_back(Operation(OperationCode::PushFlowStack, Immediate(target)));
         break;
     }
     case OpCode::Id::PBK: {
@@ -108,7 +108,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
         // using SYNC on a PBK address will kill the shader execution. We don't emulate this because
         // it's very unlikely a driver will emit such invalid shader.
         const u32 target = pc + instr.bra.GetBranchTarget();
-        bb.push_back(Operation(OperationCode::Pbk, Immediate(target)));
+        bb.push_back(Operation(OperationCode::PushFlowStack, Immediate(target)));
         break;
     }
     case OpCode::Id::SYNC: {
@@ -117,7 +117,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
                              static_cast<u32>(cc));
 
         // The SYNC opcode jumps to the address previously set by the SSY opcode
-        bb.push_back(Operation(OperationCode::Sync));
+        bb.push_back(Operation(OperationCode::PopFlowStack));
         break;
     }
     case OpCode::Id::BRK: {
@@ -126,7 +126,7 @@ u32 ShaderIR::DecodeOther(BasicBlock& bb, u32 pc) {
                              static_cast<u32>(cc));
 
         // The BRK opcode jumps to the address previously set by the PBK opcode
-        bb.push_back(Operation(OperationCode::Brk));
+        bb.push_back(Operation(OperationCode::PopFlowStack));
         break;
     }
     case OpCode::Id::IPA: {