diff options
| author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2018-12-17 22:49:48 +0100 |
|---|---|---|
| committer | ReinUsesLisp <reinuseslisp@airmail.cc> | 2019-01-15 21:54:52 +0100 |
| commit | 210620ff314c774cd0da5a6b50501dec45914751 (patch) | |
| tree | ebe61d192550b2bdfab39bf82c27f0f86eeddbfe /src/video_core/shader/decode | |
| parent | shader_decode: Implement XMAD (diff) | |
| download | yuzu-210620ff314c774cd0da5a6b50501dec45914751.tar yuzu-210620ff314c774cd0da5a6b50501dec45914751.tar.gz yuzu-210620ff314c774cd0da5a6b50501dec45914751.tar.bz2 yuzu-210620ff314c774cd0da5a6b50501dec45914751.tar.lz yuzu-210620ff314c774cd0da5a6b50501dec45914751.tar.xz yuzu-210620ff314c774cd0da5a6b50501dec45914751.tar.zst yuzu-210620ff314c774cd0da5a6b50501dec45914751.zip | |
Diffstat (limited to 'src/video_core/shader/decode')
| -rw-r--r-- | src/video_core/shader/decode/arithmetic_integer.cpp | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/video_core/shader/decode/arithmetic_integer.cpp b/src/video_core/shader/decode/arithmetic_integer.cpp index d01336e0e..d494af736 100644 --- a/src/video_core/shader/decode/arithmetic_integer.cpp +++ b/src/video_core/shader/decode/arithmetic_integer.cpp @@ -41,6 +41,21 @@ u32 ShaderIR::DecodeArithmeticInteger(BasicBlock& bb, u32 pc) { SetRegister(bb, instr.gpr0, Operation(OperationCode::IAdd, PRECISE, op_a, op_b)); break; } + case OpCode::Id::ISCADD_C: + case OpCode::Id::ISCADD_R: + case OpCode::Id::ISCADD_IMM: { + UNIMPLEMENTED_IF_MSG(instr.generates_cc, + "Condition codes generation in ISCADD is not implemented"); + + op_a = GetOperandAbsNegInteger(op_a, false, instr.alu_integer.negate_a, true); + op_b = GetOperandAbsNegInteger(op_b, false, instr.alu_integer.negate_b, true); + + const Node shift = Immediate(static_cast<u32>(instr.alu_integer.shift_amount)); + const Node shifted_a = Operation(OperationCode::ILogicalShiftLeft, NO_PRECISE, op_a, shift); + const Node value = Operation(OperationCode::IAdd, NO_PRECISE, shifted_a, op_b); + SetRegister(bb, instr.gpr0, value); + break; + } case OpCode::Id::SEL_C: case OpCode::Id::SEL_R: case OpCode::Id::SEL_IMM: { |