diff options
author | Lioncash <mathew1800@gmail.com> | 2019-10-24 03:26:07 +0200 |
---|---|---|
committer | Lioncash <mathew1800@gmail.com> | 2019-10-24 05:00:31 +0200 |
commit | 1f5401c89c922a0ff5f6da131675fcdb5c73c5a5 (patch) | |
tree | af762d898b3b02c9f1cdd88a8e2743afc29090d5 /src/video_core/shader/decode/arithmetic_integer.cpp | |
parent | Merge pull request #3022 from DarkLordZach/azure-folder-rename (diff) | |
download | yuzu-1f5401c89c922a0ff5f6da131675fcdb5c73c5a5.tar yuzu-1f5401c89c922a0ff5f6da131675fcdb5c73c5a5.tar.gz yuzu-1f5401c89c922a0ff5f6da131675fcdb5c73c5a5.tar.bz2 yuzu-1f5401c89c922a0ff5f6da131675fcdb5c73c5a5.tar.lz yuzu-1f5401c89c922a0ff5f6da131675fcdb5c73c5a5.tar.xz yuzu-1f5401c89c922a0ff5f6da131675fcdb5c73c5a5.tar.zst yuzu-1f5401c89c922a0ff5f6da131675fcdb5c73c5a5.zip |
Diffstat (limited to 'src/video_core/shader/decode/arithmetic_integer.cpp')
-rw-r--r-- | src/video_core/shader/decode/arithmetic_integer.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/video_core/shader/decode/arithmetic_integer.cpp b/src/video_core/shader/decode/arithmetic_integer.cpp index b73f6536e..a33d242e9 100644 --- a/src/video_core/shader/decode/arithmetic_integer.cpp +++ b/src/video_core/shader/decode/arithmetic_integer.cpp @@ -144,7 +144,7 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) { case OpCode::Id::ICMP_IMM: { const Node zero = Immediate(0); - const auto [op_b, test] = [&]() -> std::pair<Node, Node> { + const auto [op_rhs, test] = [&]() -> std::pair<Node, Node> { switch (opcode->get().GetId()) { case OpCode::Id::ICMP_CR: return {GetConstBuffer(instr.cbuf34.index, instr.cbuf34.offset), @@ -161,10 +161,10 @@ u32 ShaderIR::DecodeArithmeticInteger(NodeBlock& bb, u32 pc) { return {zero, zero}; } }(); - const Node op_a = GetRegister(instr.gpr8); + const Node op_lhs = GetRegister(instr.gpr8); const Node comparison = GetPredicateComparisonInteger(instr.icmp.cond, instr.icmp.is_signed != 0, test, zero); - SetRegister(bb, instr.gpr0, Operation(OperationCode::Select, comparison, op_a, op_b)); + SetRegister(bb, instr.gpr0, Operation(OperationCode::Select, comparison, op_lhs, op_rhs)); break; } case OpCode::Id::LOP_C: |