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authorSubv <subv2112@gmail.com>2018-03-18 10:17:10 +0100
committerSubv <subv2112@gmail.com>2018-03-18 17:51:46 +0100
commitaa586fa26854cfe32b97aa99c2874945420bcfc4 (patch)
tree1c17173b997f694dc0bd04d516a131748b4d990d /src/video_core/gpu.h
parentGPU: Macros are specific to the Maxwell3D engine, so handle them internally. (diff)
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Diffstat (limited to 'src/video_core/gpu.h')
-rw-r--r--src/video_core/gpu.h10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/video_core/gpu.h b/src/video_core/gpu.h
index ba7781756..d2e4ff52d 100644
--- a/src/video_core/gpu.h
+++ b/src/video_core/gpu.h
@@ -6,6 +6,7 @@
#include <memory>
#include <unordered_map>
+#include <vector>
#include "common/common_types.h"
#include "video_core/engines/fermi_2d.h"
#include "video_core/engines/maxwell_3d.h"
@@ -38,8 +39,10 @@ public:
std::unique_ptr<MemoryManager> memory_manager;
private:
+ static constexpr u32 InvalidGraphMacroEntry = 0xFFFFFFFF;
+
/// Writes a single register in the engine bound to the specified subchannel
- void WriteReg(u32 method, u32 subchannel, u32 value);
+ void WriteReg(u32 method, u32 subchannel, u32 value, u32 remaining_params);
/// Mapping of command subchannels to their bound engine ids.
std::unordered_map<u32, EngineID> bound_engines;
@@ -50,6 +53,11 @@ private:
std::unique_ptr<Engines::Fermi2D> fermi_2d;
/// Compute engine
std::unique_ptr<Engines::MaxwellCompute> maxwell_compute;
+
+ /// Entry of the macro that is currently being uploaded
+ u32 current_macro_entry = InvalidGraphMacroEntry;
+ /// Code being uploaded for the current macro
+ std::vector<u32> current_macro_code;
};
} // namespace Tegra