summaryrefslogtreecommitdiffstats
path: root/src/shader_recompiler/frontend/ir/ir_emitter.h
diff options
context:
space:
mode:
authorameerj <52414509+ameerj@users.noreply.github.com>2021-03-11 04:42:17 +0100
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:23 +0200
commitba8c1d2eb479d04b2b0d847efd67468b688765d4 (patch)
treec92c17f08ed3b313bbdb66917767ef8074d43c92 /src/shader_recompiler/frontend/ir/ir_emitter.h
parentshader: Partial implementation of LDC (diff)
downloadyuzu-ba8c1d2eb479d04b2b0d847efd67468b688765d4.tar
yuzu-ba8c1d2eb479d04b2b0d847efd67468b688765d4.tar.gz
yuzu-ba8c1d2eb479d04b2b0d847efd67468b688765d4.tar.bz2
yuzu-ba8c1d2eb479d04b2b0d847efd67468b688765d4.tar.lz
yuzu-ba8c1d2eb479d04b2b0d847efd67468b688765d4.tar.xz
yuzu-ba8c1d2eb479d04b2b0d847efd67468b688765d4.tar.zst
yuzu-ba8c1d2eb479d04b2b0d847efd67468b688765d4.zip
Diffstat (limited to '')
-rw-r--r--src/shader_recompiler/frontend/ir/ir_emitter.h19
1 files changed, 13 insertions, 6 deletions
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.h b/src/shader_recompiler/frontend/ir/ir_emitter.h
index e4d110540..5cfe1a54a 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.h
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.h
@@ -140,14 +140,21 @@ public:
[[nodiscard]] F16F32F64 FPCeil(const F16F32F64& value, FpControl control = {});
[[nodiscard]] F16F32F64 FPTrunc(const F16F32F64& value, FpControl control = {});
- [[nodiscard]] U1 FPEqual(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered = true);
- [[nodiscard]] U1 FPNotEqual(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered = true);
- [[nodiscard]] U1 FPLessThan(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered = true);
- [[nodiscard]] U1 FPGreaterThan(const F16F32F64& lhs, const F16F32F64& rhs, bool ordered = true);
+ [[nodiscard]] U1 FPEqual(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control = {},
+ bool ordered = true);
+ [[nodiscard]] U1 FPNotEqual(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control = {},
+ bool ordered = true);
+ [[nodiscard]] U1 FPLessThan(const F16F32F64& lhs, const F16F32F64& rhs, FpControl control = {},
+ bool ordered = true);
+ [[nodiscard]] U1 FPGreaterThan(const F16F32F64& lhs, const F16F32F64& rhs,
+ FpControl control = {}, bool ordered = true);
[[nodiscard]] U1 FPLessThanEqual(const F16F32F64& lhs, const F16F32F64& rhs,
- bool ordered = true);
+ FpControl control = {}, bool ordered = true);
[[nodiscard]] U1 FPGreaterThanEqual(const F16F32F64& lhs, const F16F32F64& rhs,
- bool ordered = true);
+ FpControl control = {}, bool ordered = true);
+ [[nodiscard]] U1 FPIsNan(const F32& value);
+ [[nodiscard]] U1 FPOrdered(const F32& lhs, const F32& rhs);
+ [[nodiscard]] U1 FPUnordered(const F32& lhs, const F32& rhs);
[[nodiscard]] U32U64 IAdd(const U32U64& a, const U32U64& b);
[[nodiscard]] U32U64 ISub(const U32U64& a, const U32U64& b);