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authorjam1garner <8260240+jam1garner@users.noreply.github.com>2021-11-22 03:18:56 +0100
committerjam1garner <8260240+jam1garner@users.noreply.github.com>2021-11-22 03:18:56 +0100
commitc8a67a725de6481c891d5bfe1b83fcb6340c88a3 (patch)
tree9211464997cc2f241a56fd88b810f8bd599c9a73 /src/core/arm
parentarm: dynarmic: Implement icache op handling for 'ic ivau' instruction (diff)
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Diffstat (limited to 'src/core/arm')
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 587fffb34..8fe83413c 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -98,6 +98,9 @@ public:
return;
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
+ parent.ClearInstructionCache();
+ return;
+
case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
default:
LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation");