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authorbunnei <bunneidev@gmail.com>2018-03-19 03:35:47 +0100
committerGitHub <noreply@github.com>2018-03-19 03:35:47 +0100
commit23a0d2d7b77fa619edc7d69d0162bd3071b67b4b (patch)
tree85f20b5e8bbd0b1b2b6e28eac6224908a0f3b7fe /src/core/arm
parentMerge pull request #250 from bunnei/buffer-dequeue-wait (diff)
parentImplements citra-emu/citra#3184 (diff)
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Diffstat (limited to 'src/core/arm')
-rw-r--r--src/core/arm/arm_interface.h29
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic.cpp19
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic.h5
-rw-r--r--src/core/arm/unicorn/arm_unicorn.cpp9
-rw-r--r--src/core/arm/unicorn/arm_unicorn.h4
5 files changed, 31 insertions, 35 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index 6667c7dba..32ff3c345 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -25,19 +25,11 @@ public:
VAddr tls_address;
};
- /**
- * Runs the CPU for the given number of instructions
- * @param num_instructions Number of instructions to run
- */
- void Run(int num_instructions) {
- ExecuteInstructions(num_instructions);
- this->num_instructions += num_instructions;
- }
+ /// Runs the CPU until an event happens
+ virtual void Run() = 0;
/// Step CPU by one instruction
- void Step() {
- Run(1);
- }
+ virtual void Step() = 0;
/// Maps a backing memory region for the CPU
virtual void MapBackingMemory(VAddr address, size_t size, u8* memory,
@@ -126,19 +118,4 @@ public:
/// Prepare core for thread reschedule (if needed to correctly handle state)
virtual void PrepareReschedule() = 0;
-
- /// Getter for num_instructions
- u64 GetNumInstructions() const {
- return num_instructions;
- }
-
-protected:
- /**
- * Executes the given number of instructions
- * @param num_instructions Number of instructions to executes
- */
- virtual void ExecuteInstructions(int num_instructions) = 0;
-
-private:
- u64 num_instructions = 0; ///< Number of instructions executed
};
diff --git a/src/core/arm/dynarmic/arm_dynarmic.cpp b/src/core/arm/dynarmic/arm_dynarmic.cpp
index 0902c6df3..7d83f9717 100644
--- a/src/core/arm/dynarmic/arm_dynarmic.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic.cpp
@@ -122,11 +122,22 @@ std::unique_ptr<Dynarmic::A64::Jit> MakeJit(const std::unique_ptr<ARM_Dynarmic_C
return std::make_unique<Dynarmic::A64::Jit>(config);
}
+void ARM_Dynarmic::Run() {
+ ASSERT(Memory::GetCurrentPageTable() == current_page_table);
+
+ jit->Run();
+}
+
+void ARM_Dynarmic::Step() {
+ cb->InterpreterFallback(jit->GetPC(), 1);
+}
+
ARM_Dynarmic::ARM_Dynarmic()
: cb(std::make_unique<ARM_Dynarmic_Callbacks>(*this)), jit(MakeJit(cb)) {
ARM_Interface::ThreadContext ctx;
inner_unicorn.SaveContext(ctx);
LoadContext(ctx);
+ PageTableChanged();
}
ARM_Dynarmic::~ARM_Dynarmic() = default;
@@ -189,13 +200,6 @@ void ARM_Dynarmic::SetTlsAddress(u64 address) {
cb->tpidrro_el0 = address;
}
-void ARM_Dynarmic::ExecuteInstructions(int num_instructions) {
- cb->ticks_remaining = num_instructions;
- jit->Run();
- CoreTiming::AddTicks(num_instructions - cb->num_interpreted_instructions);
- cb->num_interpreted_instructions = 0;
-}
-
void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
ctx.cpu_registers = jit->GetRegisters();
ctx.sp = jit->GetSP();
@@ -228,4 +232,5 @@ void ARM_Dynarmic::ClearInstructionCache() {
void ARM_Dynarmic::PageTableChanged() {
jit = MakeJit(cb);
+ current_page_table = Memory::GetCurrentPageTable();
}
diff --git a/src/core/arm/dynarmic/arm_dynarmic.h b/src/core/arm/dynarmic/arm_dynarmic.h
index fd1a44802..128669d01 100644
--- a/src/core/arm/dynarmic/arm_dynarmic.h
+++ b/src/core/arm/dynarmic/arm_dynarmic.h
@@ -29,6 +29,8 @@ public:
u32 GetVFPReg(int index) const override;
void SetVFPReg(int index, u32 value) override;
u32 GetCPSR() const override;
+ void Run() override;
+ void Step() override;
void SetCPSR(u32 cpsr) override;
VAddr GetTlsAddress() const override;
void SetTlsAddress(VAddr address) override;
@@ -37,7 +39,6 @@ public:
void LoadContext(const ThreadContext& ctx) override;
void PrepareReschedule() override;
- void ExecuteInstructions(int num_instructions) override;
void ClearInstructionCache() override;
void PageTableChanged() override;
@@ -47,4 +48,6 @@ private:
std::unique_ptr<ARM_Dynarmic_Callbacks> cb;
std::unique_ptr<Dynarmic::A64::Jit> jit;
ARM_Unicorn inner_unicorn;
+
+ Memory::PageTable* current_page_table = nullptr;
};
diff --git a/src/core/arm/unicorn/arm_unicorn.cpp b/src/core/arm/unicorn/arm_unicorn.cpp
index 162c766fd..bd98cb160 100644
--- a/src/core/arm/unicorn/arm_unicorn.cpp
+++ b/src/core/arm/unicorn/arm_unicorn.cpp
@@ -2,6 +2,7 @@
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
+#include <algorithm>
#include <unicorn/arm64.h>
#include "common/assert.h"
#include "common/microprofile.h"
@@ -153,6 +154,14 @@ void ARM_Unicorn::SetTlsAddress(VAddr base) {
CHECKED(uc_reg_write(uc, UC_ARM64_REG_TPIDRRO_EL0, &base));
}
+void ARM_Unicorn::Run() {
+ ExecuteInstructions(std::max(CoreTiming::GetDowncount(), 0));
+}
+
+void ARM_Unicorn::Step() {
+ ExecuteInstructions(1);
+}
+
MICROPROFILE_DEFINE(ARM_Jit, "ARM JIT", "ARM JIT", MP_RGB(255, 64, 64));
void ARM_Unicorn::ExecuteInstructions(int num_instructions) {
diff --git a/src/core/arm/unicorn/arm_unicorn.h b/src/core/arm/unicorn/arm_unicorn.h
index 00b5b1865..b99b58e4c 100644
--- a/src/core/arm/unicorn/arm_unicorn.h
+++ b/src/core/arm/unicorn/arm_unicorn.h
@@ -30,7 +30,9 @@ public:
void SaveContext(ThreadContext& ctx) override;
void LoadContext(const ThreadContext& ctx) override;
void PrepareReschedule() override;
- void ExecuteInstructions(int num_instructions) override;
+ void ExecuteInstructions(int num_instructions);
+ void Run() override;
+ void Step() override;
void ClearInstructionCache() override;
void PageTableChanged() override{};