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authorwwylele <wwylele@gmail.com>2016-06-27 20:38:49 +0200
committerwwylele <wwylele@gmail.com>2016-08-27 15:38:06 +0200
commit2161f52661f9866161165db480594672307940ad (patch)
tree5a8bb26803b0b521e9d1dcb8570210d8d5b393a8 /src/core/arm
parentMemory: add ReadCString function (diff)
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Diffstat (limited to 'src/core/arm')
-rw-r--r--src/core/arm/arm_interface.h3
-rw-r--r--src/core/arm/dyncom/arm_dyncom.cpp6
-rw-r--r--src/core/arm/dyncom/arm_dyncom.h2
3 files changed, 11 insertions, 0 deletions
diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index d8abe5aeb..de5e9c8fa 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -32,6 +32,9 @@ public:
Run(1);
}
+ /// Clear all instruction cache
+ virtual void ClearInstructionCache() = 0;
+
/**
* Set the Program Counter to an address
* @param addr Address to set PC to
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index 13492a08b..ab77da965 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -12,6 +12,7 @@
#include "core/arm/dyncom/arm_dyncom.h"
#include "core/arm/dyncom/arm_dyncom_interpreter.h"
#include "core/arm/dyncom/arm_dyncom_run.h"
+#include "core/arm/dyncom/arm_dyncom_trans.h"
#include "core/core.h"
#include "core/core_timing.h"
@@ -23,6 +24,11 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
ARM_DynCom::~ARM_DynCom() {
}
+void ARM_DynCom::ClearInstructionCache() {
+ state->instruction_cache.clear();
+ trans_cache_buf_top = 0;
+}
+
void ARM_DynCom::SetPC(u32 pc) {
state->Reg[15] = pc;
}
diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h
index 3664fd728..e763abc24 100644
--- a/src/core/arm/dyncom/arm_dyncom.h
+++ b/src/core/arm/dyncom/arm_dyncom.h
@@ -21,6 +21,8 @@ public:
ARM_DynCom(PrivilegeMode initial_mode);
~ARM_DynCom();
+ void ClearInstructionCache() override;
+
void SetPC(u32 pc) override;
u32 GetPC() const override;
u32 GetReg(int index) const override;