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| author | Lioncash <mathew1800@gmail.com> | 2015-05-24 02:51:02 +0200 |
|---|---|---|
| committer | Lioncash <mathew1800@gmail.com> | 2015-05-24 02:51:02 +0200 |
| commit | 6278937a289fee07102e6d3474074d723372f2d5 (patch) | |
| tree | cd660f784d8700268bb7d43a98db5b4151ae10c6 /src/core/arm/skyeye_common/armdefs.h | |
| parent | Merge pull request #805 from lioncash/warn (diff) | |
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Diffstat (limited to 'src/core/arm/skyeye_common/armdefs.h')
| -rw-r--r-- | src/core/arm/skyeye_common/armdefs.h | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/src/core/arm/skyeye_common/armdefs.h b/src/core/arm/skyeye_common/armdefs.h index 470f9508d..08ece69b6 100644 --- a/src/core/arm/skyeye_common/armdefs.h +++ b/src/core/arm/skyeye_common/armdefs.h @@ -262,6 +262,34 @@ enum ConditionCode { NV = 15, }; +// Flags for use with the APSR. +enum : u32 { + NBIT = (1U << 31U), + ZBIT = (1 << 30), + CBIT = (1 << 29), + VBIT = (1 << 28), + QBIT = (1 << 27), + JBIT = (1 << 24), + EBIT = (1 << 9), + ABIT = (1 << 8), + IBIT = (1 << 7), + FBIT = (1 << 6), + TBIT = (1 << 5), + + // Masks for groups of bits in the APSR. + MODEBITS = 0x1F, + INTBITS = 0x1C0, +}; + +// Values for Emulate. +enum { + STOP = 0, // Stop + CHANGEMODE = 1, // Change mode + ONCE = 2, // Execute just one iteration + RUN = 3 // Continuous execution +}; + + extern bool AddOverflow(ARMword, ARMword, ARMword); extern bool SubOverflow(ARMword, ARMword, ARMword); |