summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorameerj <52414509+ameerj@users.noreply.github.com>2021-05-26 02:55:06 +0200
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:36 +0200
commitb95716e5431e7ddb05239c31080c01aab24a13ac (patch)
tree0de79d8166ee7ebbdb10bcc3a830bf0580d0de3d
parentglsl: Fix floating point compare ops (diff)
downloadyuzu-b95716e5431e7ddb05239c31080c01aab24a13ac.tar
yuzu-b95716e5431e7ddb05239c31080c01aab24a13ac.tar.gz
yuzu-b95716e5431e7ddb05239c31080c01aab24a13ac.tar.bz2
yuzu-b95716e5431e7ddb05239c31080c01aab24a13ac.tar.lz
yuzu-b95716e5431e7ddb05239c31080c01aab24a13ac.tar.xz
yuzu-b95716e5431e7ddb05239c31080c01aab24a13ac.tar.zst
yuzu-b95716e5431e7ddb05239c31080c01aab24a13ac.zip
-rw-r--r--src/shader_recompiler/backend/glsl/emit_glsl.cpp37
-rw-r--r--src/shader_recompiler/backend/glsl/emit_glsl_not_implemented.cpp24
-rw-r--r--src/shader_recompiler/backend/glsl/reg_alloc.cpp3
-rw-r--r--src/shader_recompiler/backend/glsl/reg_alloc.h10
4 files changed, 53 insertions, 21 deletions
diff --git a/src/shader_recompiler/backend/glsl/emit_glsl.cpp b/src/shader_recompiler/backend/glsl/emit_glsl.cpp
index e5aaf81a7..a8e53cf66 100644
--- a/src/shader_recompiler/backend/glsl/emit_glsl.cpp
+++ b/src/shader_recompiler/backend/glsl/emit_glsl.cpp
@@ -98,18 +98,33 @@ void EmitInst(EmitContext& ctx, IR::Inst* inst) {
throw LogicError("Invalid opcode {}", inst->GetOpcode());
}
-void Precolor(EmitContext& ctx, const IR::Program& program) {
+bool IsReference(IR::Inst& inst) {
+ return inst.GetOpcode() == IR::Opcode::Reference;
+}
+
+void PrecolorInst(IR::Inst& phi) {
+ // Insert phi moves before references to avoid overwritting other phis
+ const size_t num_args{phi.NumArgs()};
+ for (size_t i = 0; i < num_args; ++i) {
+ IR::Block& phi_block{*phi.PhiBlock(i)};
+ auto it{std::find_if_not(phi_block.rbegin(), phi_block.rend(), IsReference).base()};
+ IR::IREmitter ir{phi_block, it};
+ const IR::Value arg{phi.Arg(i)};
+ if (arg.IsImmediate()) {
+ ir.PhiMove(phi, arg);
+ } else {
+ ir.PhiMove(phi, IR::Value{&RegAlloc::AliasInst(*arg.Inst())});
+ }
+ }
+ for (size_t i = 0; i < num_args; ++i) {
+ IR::IREmitter{*phi.PhiBlock(i)}.Reference(IR::Value{&phi});
+ }
+}
+
+void Precolor(const IR::Program& program) {
for (IR::Block* const block : program.blocks) {
for (IR::Inst& phi : block->Instructions() | std::views::take_while(IR::IsPhi)) {
- ctx.Add("{};", ctx.reg_alloc.Define(phi, phi.Arg(0).Type()));
- const size_t num_args{phi.NumArgs()};
- for (size_t i = 0; i < num_args; ++i) {
- IR::IREmitter{*phi.PhiBlock(i)}.PhiMove(phi, phi.Arg(i));
- }
- // Add reference to the phi node on the phi predecessor to avoid overwritting it
- for (size_t i = 0; i < num_args; ++i) {
- IR::IREmitter{*phi.PhiBlock(i)}.Reference(IR::Value{&phi});
- }
+ PrecolorInst(phi);
}
}
}
@@ -158,7 +173,7 @@ void EmitCode(EmitContext& ctx, const IR::Program& program) {
std::string EmitGLSL(const Profile& profile, const RuntimeInfo&, IR::Program& program,
Bindings& bindings) {
EmitContext ctx{program, bindings, profile};
- Precolor(ctx, program);
+ Precolor(program);
EmitCode(ctx, program);
return ctx.code;
}
diff --git a/src/shader_recompiler/backend/glsl/emit_glsl_not_implemented.cpp b/src/shader_recompiler/backend/glsl/emit_glsl_not_implemented.cpp
index d67a1d81f..b37b3c76d 100644
--- a/src/shader_recompiler/backend/glsl/emit_glsl_not_implemented.cpp
+++ b/src/shader_recompiler/backend/glsl/emit_glsl_not_implemented.cpp
@@ -19,8 +19,15 @@ static void NotImplemented() {
throw NotImplementedException("GLSL instruction");
}
-void EmitPhi(EmitContext& ctx, IR::Inst& inst) {
- // NotImplemented();
+void EmitPhi(EmitContext& ctx, IR::Inst& phi) {
+ const size_t num_args{phi.NumArgs()};
+ for (size_t i = 0; i < num_args; ++i) {
+ ctx.reg_alloc.Consume(phi.Arg(i));
+ }
+ if (!phi.Definition<Id>().is_valid) {
+ // The phi node wasn't forward defined
+ ctx.Add("{};", ctx.reg_alloc.Define(phi, phi.Arg(0).Type()));
+ }
}
void EmitVoid(EmitContext& ctx) {
@@ -31,11 +38,18 @@ void EmitReference(EmitContext&) {
// NotImplemented();
}
-void EmitPhiMove(EmitContext& ctx, const IR::Value& phi, const IR::Value& value) {
- if (phi == value) {
+void EmitPhiMove(EmitContext& ctx, const IR::Value& phi_value, const IR::Value& value) {
+ IR::Inst& phi{RegAlloc::AliasInst(*phi_value.Inst())};
+ if (!phi.Definition<Id>().is_valid) {
+ // The phi node wasn't forward defined
+ ctx.Add("{};", ctx.reg_alloc.Define(phi, phi.Arg(0).Type()));
+ }
+ const auto phi_reg{ctx.reg_alloc.Consume(IR::Value{&phi})};
+ const auto val_reg{ctx.reg_alloc.Consume(value)};
+ if (phi_reg == val_reg) {
return;
}
- ctx.Add("{}={};", ctx.reg_alloc.Consume(phi), ctx.reg_alloc.Consume(value));
+ ctx.Add("{}={};", phi_reg, val_reg);
}
void EmitBranch(EmitContext& ctx, std::string_view label) {
diff --git a/src/shader_recompiler/backend/glsl/reg_alloc.cpp b/src/shader_recompiler/backend/glsl/reg_alloc.cpp
index 3de4c1172..c60a87d91 100644
--- a/src/shader_recompiler/backend/glsl/reg_alloc.cpp
+++ b/src/shader_recompiler/backend/glsl/reg_alloc.cpp
@@ -146,10 +146,11 @@ Id RegAlloc::Alloc() {
}
register_use[reg] = true;
Id ret{};
- ret.index.Assign(static_cast<u32>(reg));
+ ret.is_valid.Assign(1);
ret.is_long.Assign(0);
ret.is_spill.Assign(0);
ret.is_condition_code.Assign(0);
+ ret.index.Assign(static_cast<u32>(reg));
return ret;
}
}
diff --git a/src/shader_recompiler/backend/glsl/reg_alloc.h b/src/shader_recompiler/backend/glsl/reg_alloc.h
index 9f2ff8718..419e1e761 100644
--- a/src/shader_recompiler/backend/glsl/reg_alloc.h
+++ b/src/shader_recompiler/backend/glsl/reg_alloc.h
@@ -33,10 +33,12 @@ enum class Type : u32 {
struct Id {
union {
u32 raw;
- BitField<0, 29, u32> index;
- BitField<29, 1, u32> is_long;
- BitField<30, 1, u32> is_spill;
- BitField<31, 1, u32> is_condition_code;
+ BitField<0, 1, u32> is_valid;
+ BitField<1, 1, u32> is_long;
+ BitField<2, 1, u32> is_spill;
+ BitField<3, 1, u32> is_condition_code;
+ BitField<4, 1, u32> is_null;
+ BitField<5, 27, u32> index;
};
bool operator==(Id rhs) const noexcept {