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authorMerryMage <MerryMage@users.noreply.github.com>2017-02-18 20:45:24 +0100
committerMerryMage <MerryMage@users.noreply.github.com>2017-02-18 21:04:54 +0100
commitb1253881524ee6681399d6d79756d92e9d052d05 (patch)
tree138cf5b468c8983004e01fe015ea3b3e397aa230
parentMerge pull request #2482 from yuriks/pica-refactor (diff)
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-rw-r--r--src/core/arm/dyncom/arm_dyncom_interpreter.cpp8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
index 67c45640a..273bc8167 100644
--- a/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
+++ b/src/core/arm/dyncom/arm_dyncom_interpreter.cpp
@@ -3928,13 +3928,13 @@ SXTB16_INST : {
if (inst_cream->Rn == 15) {
u32 lo = (u32)(s8)rm_val;
u32 hi = (u32)(s8)(rm_val >> 16);
- RD = (lo | (hi << 16));
+ RD = (lo & 0xFFFF) | (hi << 16);
}
// SXTAB16
else {
- u32 lo = (rn_val & 0xFFFF) + (u32)(s8)(rm_val & 0xFF);
- u32 hi = ((rn_val >> 16) & 0xFFFF) + (u32)(s8)((rm_val >> 16) & 0xFF);
- RD = (lo | (hi << 16));
+ u32 lo = rn_val + (u32)(s8)(rm_val & 0xFF);
+ u32 hi = (rn_val >> 16) + (u32)(s8)((rm_val >> 16) & 0xFF);
+ RD = (lo & 0xFFFF) | (hi << 16);
}
}