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authorjam1garner <8260240+jam1garner@users.noreply.github.com>2021-11-22 03:10:14 +0100
committerjam1garner <8260240+jam1garner@users.noreply.github.com>2021-11-22 03:10:14 +0100
commit84eb3e7d02d386bc90eb4a6c6b6e33eea33a42e2 (patch)
treee70948fdb0d8ea9d761cb91d590f6940f5ace625
parentMerge pull request #7395 from Morph1984/resolve-comments (diff)
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-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp18
1 files changed, 18 insertions, 0 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 4e73cc03a..587fffb34 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -86,6 +86,24 @@ public:
num_instructions, MemoryReadCode(pc));
}
+ void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
+ VAddr value) override {
+ constexpr u64 ICACHE_LINE_SIZE = 64;
+ u64 cache_line_start;
+
+ switch (op) {
+ case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU:
+ cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
+ parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
+ return;
+
+ case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
+ case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
+ default:
+ LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation");
+ }
+ }
+
void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
switch (exception) {
case Dynarmic::A64::Exception::WaitForInterrupt: