summaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorReinUsesLisp <reinuseslisp@airmail.cc>2021-02-16 23:48:58 +0100
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:22 +0200
commit3a59fffaa16838985f9f953f30d1af4aa0f86252 (patch)
tree63d8dbf8cfb55da7c08233655fb6e87df18c4030
parentspirv: Initial bindings support (diff)
downloadyuzu-3a59fffaa16838985f9f953f30d1af4aa0f86252.tar
yuzu-3a59fffaa16838985f9f953f30d1af4aa0f86252.tar.gz
yuzu-3a59fffaa16838985f9f953f30d1af4aa0f86252.tar.bz2
yuzu-3a59fffaa16838985f9f953f30d1af4aa0f86252.tar.lz
yuzu-3a59fffaa16838985f9f953f30d1af4aa0f86252.tar.xz
yuzu-3a59fffaa16838985f9f953f30d1af4aa0f86252.tar.zst
yuzu-3a59fffaa16838985f9f953f30d1af4aa0f86252.zip
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.cpp4
-rw-r--r--src/shader_recompiler/backend/spirv/emit_spirv.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.cpp b/src/shader_recompiler/backend/spirv/emit_spirv.cpp
index c79c09774..55018332e 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.cpp
@@ -180,8 +180,8 @@ Id EmitSPIRV::EmitPhi(EmitContext& ctx, IR::Inst* inst) {
void EmitSPIRV::EmitVoid(EmitContext&) {}
-void EmitSPIRV::EmitIdentity(EmitContext&) {
- throw NotImplementedException("SPIR-V Instruction");
+Id EmitSPIRV::EmitIdentity(EmitContext& ctx, const IR::Value& value) {
+ return ctx.Def(value);
}
void EmitSPIRV::EmitGetZeroFromOp(EmitContext&) {
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index a5d0e1ec0..8bde82613 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -23,7 +23,7 @@ private:
// Microinstruction emitters
Id EmitPhi(EmitContext& ctx, IR::Inst* inst);
void EmitVoid(EmitContext& ctx);
- void EmitIdentity(EmitContext& ctx);
+ Id EmitIdentity(EmitContext& ctx, const IR::Value& value);
void EmitBranch(EmitContext& ctx, IR::Block* label);
void EmitBranchConditional(EmitContext& ctx, Id condition, IR::Block* true_label,
IR::Block* false_label);