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authorameerj <52414509+ameerj@users.noreply.github.com>2021-03-01 06:25:15 +0100
committerameerj <52414509+ameerj@users.noreply.github.com>2021-07-23 03:51:22 +0200
commitbec7d3111d3de2a7a8384b1e761bc3692afef9c7 (patch)
tree9439129aa03a181b411da1da2a8cf28e6f5b5d79
parentshader: Implement ICMP (diff)
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Diffstat (limited to '')
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/integer_minimum_maximum.cpp2
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp4
-rw-r--r--src/shader_recompiler/frontend/maxwell/translate/impl/select_source_with_predicate.cpp4
3 files changed, 5 insertions, 5 deletions
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_minimum_maximum.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_minimum_maximum.cpp
index 12c6aae3d..5303db612 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_minimum_maximum.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_minimum_maximum.cpp
@@ -23,7 +23,7 @@ void IMNMX(TranslatorVisitor& v, u64 insn, const IR::U32& op_b) {
throw NotImplementedException("IMNMX.MODE");
}
- IR::U1 pred = v.ir.GetPred(imnmx.pred);
+ IR::U1 pred{v.ir.GetPred(imnmx.pred)};
const IR::U32 op_a{v.X(imnmx.src_reg)};
IR::U32 min;
IR::U32 max;
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp
index a34ccb851..4025b1358 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_right.cpp
@@ -16,7 +16,7 @@ void SHR(TranslatorVisitor& v, u64 insn, const IR::U32& shift) {
BitField<39, 1, u64> is_wrapped;
BitField<40, 1, u64> brev;
BitField<43, 1, u64> xmode;
- BitField<48, 1, u64> is_arithmetic;
+ BitField<48, 1, u64> is_signed;
} const shr{insn};
if (shr.xmode != 0) {
@@ -29,7 +29,7 @@ void SHR(TranslatorVisitor& v, u64 insn, const IR::U32& shift) {
}
IR::U32 result;
const IR::U32 safe_shift = shr.is_wrapped == 0 ? shift : v.ir.BitwiseAnd(shift, v.ir.Imm32(31));
- if (shr.is_arithmetic == 1) {
+ if (shr.is_signed == 1) {
result = IR::U32{v.ir.ShiftRightArithmetic(base, safe_shift)};
} else {
result = IR::U32{v.ir.ShiftRightLogical(base, safe_shift)};
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/select_source_with_predicate.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/select_source_with_predicate.cpp
index 25fc6b437..93baa75a9 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/select_source_with_predicate.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/select_source_with_predicate.cpp
@@ -13,13 +13,13 @@ void SEL(TranslatorVisitor& v, u64 insn, const IR::U32& src) {
union {
u64 raw;
BitField<0, 8, IR::Reg> dest_reg;
- BitField<8, 8, IR::Reg> op_a;
+ BitField<8, 8, IR::Reg> src_reg;
BitField<39, 3, IR::Pred> pred;
BitField<42, 1, u64> neg_pred;
} const sel{insn};
const IR::U1 pred = v.ir.GetPred(sel.pred);
- IR::U32 op_a{v.X(sel.op_a)};
+ IR::U32 op_a{v.X(sel.src_reg)};
IR::U32 op_b{src};
if (sel.neg_pred != 0) {
std::swap(op_a, op_b);