#pragma once #include #include #include #include #include "common/common_types.h" namespace Tegra { namespace Engines { class Maxwell3D; class KeplerCompute; } // namespace Engines class MemoryManager; namespace Control { struct ChannelState; } } // namespace Tegra namespace VideoCommon { class ChannelInfo { public: ChannelInfo() = delete; ChannelInfo(Tegra::Control::ChannelState& state); ChannelInfo(const ChannelInfo& state) = delete; ChannelInfo& operator=(const ChannelInfo&) = delete; ChannelInfo(ChannelInfo&& other) = default; ChannelInfo& operator=(ChannelInfo&& other) = default; Tegra::Engines::Maxwell3D& maxwell3d; Tegra::Engines::KeplerCompute& kepler_compute; Tegra::MemoryManager& gpu_memory; }; template class ChannelSetupCaches { public: /// Operations for seting the channel of execution. virtual ~ChannelSetupCaches(); /// Create channel state. virtual void CreateChannel(Tegra::Control::ChannelState& channel); /// Bind a channel for execution. void BindToChannel(s32 id); /// Erase channel's state. void EraseChannel(s32 id); Tegra::MemoryManager* GetFromID(size_t id) const { std::unique_lock lk(config_mutex); const auto ref = address_spaces.find(id); return ref->second.gpu_memory; } protected: static constexpr size_t UNSET_CHANNEL{std::numeric_limits::max()}; P* channel_state; size_t current_channel_id{UNSET_CHANNEL}; size_t current_address_space{}; Tegra::Engines::Maxwell3D* maxwell3d; Tegra::Engines::KeplerCompute* kepler_compute; Tegra::MemoryManager* gpu_memory; std::deque

channel_storage; std::deque free_channel_ids; std::unordered_map channel_map; std::vector active_channel_ids; struct AddresSpaceRef { size_t ref_count; size_t storage_id; Tegra::MemoryManager* gpu_memory; }; std::unordered_map address_spaces; mutable std::mutex config_mutex; virtual void OnGPUASRegister([[maybe_unused]] size_t map_id) {} }; } // namespace VideoCommon