// Copyright 2021 yuzu Emulator Project // Licensed under GPLv2 or any later version // Refer to the license.txt file included. #include "common/bit_field.h" #include "shader_recompiler/frontend/ir/ir_emitter.h" #include "shader_recompiler/frontend/maxwell/translate/impl/impl.h" namespace Shader::Maxwell { IR::U32 TranslatorVisitor::X(IR::Reg reg) { return ir.GetReg(reg); } IR::F32 TranslatorVisitor::F(IR::Reg reg) { return ir.BitCast(X(reg)); } void TranslatorVisitor::X(IR::Reg dest_reg, const IR::U32& value) { ir.SetReg(dest_reg, value); } void TranslatorVisitor::F(IR::Reg dest_reg, const IR::F32& value) { X(dest_reg, ir.BitCast(value)); } IR::U32 TranslatorVisitor::GetReg8(u64 insn) { union { u64 raw; BitField<8, 8, IR::Reg> index; } const reg{insn}; return X(reg.index); } IR::U32 TranslatorVisitor::GetReg20(u64 insn) { union { u64 raw; BitField<20, 8, IR::Reg> index; } const reg{insn}; return X(reg.index); } IR::U32 TranslatorVisitor::GetReg39(u64 insn) { union { u64 raw; BitField<39, 8, IR::Reg> index; } const reg{insn}; return X(reg.index); } IR::F32 TranslatorVisitor::GetFloatReg20(u64 insn) { return ir.BitCast(GetReg20(insn)); } IR::F32 TranslatorVisitor::GetFloatReg39(u64 insn) { return ir.BitCast(GetReg39(insn)); } static std::pair CbufAddr(u64 insn) { union { u64 raw; BitField<20, 14, s64> offset; BitField<34, 5, u64> binding; } const cbuf{insn}; if (cbuf.binding >= 18) { throw NotImplementedException("Out of bounds constant buffer binding {}", cbuf.binding); } if (cbuf.offset >= 0x10'000 || cbuf.offset < 0) { throw NotImplementedException("Out of bounds constant buffer offset {}", cbuf.offset); } const IR::Value binding{static_cast(cbuf.binding)}; const IR::Value byte_offset{static_cast(cbuf.offset) * 4}; return {IR::U32{binding}, IR::U32{byte_offset}}; } IR::U32 TranslatorVisitor::GetCbuf(u64 insn) { const auto[binding, byte_offset]{CbufAddr(insn)}; return ir.GetCbuf(binding, byte_offset); } IR::F32 TranslatorVisitor::GetFloatCbuf(u64 insn) { const auto[binding, byte_offset]{CbufAddr(insn)}; return ir.GetFloatCbuf(binding, byte_offset); } IR::U32 TranslatorVisitor::GetImm20(u64 insn) { union { u64 raw; BitField<20, 19, u64> value; BitField<56, 1, u64> is_negative; } const imm{insn}; if (imm.is_negative != 0) { const s64 raw{static_cast(imm.value)}; return ir.Imm32(static_cast(-(1LL << 19) + raw)); } else { return ir.Imm32(static_cast(imm.value)); } } IR::F32 TranslatorVisitor::GetFloatImm20(u64 insn) { union { u64 raw; BitField<20, 19, u64> value; BitField<56, 1, u64> is_negative; } const imm{insn}; const u32 sign_bit{imm.is_negative != 0 ? (1ULL << 31) : 0}; const u32 value{static_cast(imm.value) << 12}; return ir.Imm32(Common::BitCast(value | sign_bit)); } IR::U32 TranslatorVisitor::GetImm32(u64 insn) { union { u64 raw; BitField<20, 32, u64> value; } const imm{insn}; return ir.Imm32(static_cast(imm.value)); } IR::F32 TranslatorVisitor::GetFloatImm32(u64 insn) { union { u64 raw; BitField<20, 32, u64> value; } const imm{insn}; return ir.Imm32(Common::BitCast(static_cast(imm.value))); } void TranslatorVisitor::SetZFlag(const IR::U1& value) { ir.SetZFlag(value); } void TranslatorVisitor::SetSFlag(const IR::U1& value) { ir.SetSFlag(value); } void TranslatorVisitor::SetCFlag(const IR::U1& value) { ir.SetCFlag(value); } void TranslatorVisitor::SetOFlag(const IR::U1& value) { ir.SetOFlag(value); } void TranslatorVisitor::ResetZero() { SetZFlag(ir.Imm1(false)); } void TranslatorVisitor::ResetSFlag() { SetSFlag(ir.Imm1(false)); } void TranslatorVisitor::ResetCFlag() { SetCFlag(ir.Imm1(false)); } void TranslatorVisitor::ResetOFlag() { SetOFlag(ir.Imm1(false)); } } // namespace Shader::Maxwell