From 438a9b70ccc4345496bdd6ccc115b3528b40383c Mon Sep 17 00:00:00 2001 From: Subv Date: Mon, 4 Jun 2018 18:29:51 -0500 Subject: GPU: Added decodings for the ISCADD instructions. --- src/video_core/engines/shader_bytecode.h | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src') diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index 22c122fcc..da451c4d6 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -362,6 +362,9 @@ public: FMUL_R, FMUL_IMM, FMUL32_IMM, + ISCADD_C, // Scale and Add + ISCADD_R, + ISCADD_IMM, MUFU, // Multi-Function Operator RRO_C, // Range Reduction Operator RRO_R, @@ -405,6 +408,7 @@ public: Trivial, Arithmetic, Logic, + ScaledAdd, Ffma, Flow, Memory, @@ -528,6 +532,9 @@ private: INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"), INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"), INST("00011110--------", Id::FMUL32_IMM, Type::Arithmetic, "FMUL32_IMM"), + INST("0100110000011---", Id::ISCADD_C, Type::ScaledAdd, "ISCADD_C"), + INST("0101110000011---", Id::ISCADD_R, Type::ScaledAdd, "ISCADD_R"), + INST("0011100-00011---", Id::ISCADD_IMM, Type::ScaledAdd, "ISCADD_IMM"), INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"), INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"), INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"), -- cgit v1.2.3 From 23b1e6eded2d4af99b69d6958314db610ab23cd3 Mon Sep 17 00:00:00 2001 From: Subv Date: Mon, 4 Jun 2018 19:03:47 -0500 Subject: GPU: Implement the ISCADD shader instructions. --- src/video_core/engines/shader_bytecode.h | 16 +++++++++++++++ .../renderer_opengl/gl_shader_decompiler.cpp | 24 ++++++++++++++++++++++ 2 files changed, 40 insertions(+) (limited to 'src') diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h index da451c4d6..8d4ea3401 100644 --- a/src/video_core/engines/shader_bytecode.h +++ b/src/video_core/engines/shader_bytecode.h @@ -232,6 +232,22 @@ union Instruction { } } alu; + union { + BitField<39, 5, u64> shift_amount; + BitField<20, 19, u64> immediate_low; + BitField<56, 1, u64> immediate_high; + BitField<48, 1, u64> negate_b; + BitField<49, 1, u64> negate_a; + + s32 GetImmediate() const { + u32 immediate = static_cast(immediate_low | (immediate_high << 19)); + // Sign extend the 20-bit value. + u32 mask = 1U << (20 - 1); + return static_cast((immediate ^ mask) - mask); + } + + } iscadd; + union { BitField<48, 1, u64> negate_b; BitField<49, 1, u64> negate_c; diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp index 9943394c6..30ba9be67 100644 --- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp +++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp @@ -884,6 +884,30 @@ private: } break; } + case OpCode::Type::ScaledAdd: { + std::string op_a = regs.GetRegisterAsInteger(instr.gpr8); + + if (instr.iscadd.negate_a) + op_a = '-' + op_a; + + std::string op_b = instr.iscadd.negate_b ? "-" : ""; + + if (instr.is_b_imm) { + op_b += '(' + std::to_string(instr.iscadd.GetImmediate()) + ')'; + } else { + if (instr.is_b_gpr) { + op_b += regs.GetRegisterAsInteger(instr.gpr20); + } else { + op_b += regs.GetUniform(instr.uniform, instr.gpr0); + } + } + + std::string shift = std::to_string(instr.iscadd.shift_amount.Value()); + + regs.SetRegisterToInteger(instr.gpr0, true, 0, + "((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1); + break; + } case OpCode::Type::Ffma: { std::string op_a = regs.GetRegisterAsFloat(instr.gpr8); std::string op_b = instr.ffma.negate_b ? "-" : ""; -- cgit v1.2.3