From 6cddf9d88e7fc49919fda92bcd4235797c56f07f Mon Sep 17 00:00:00 2001 From: Subv Date: Sun, 11 Feb 2018 23:44:12 -0500 Subject: Make a GPU class in VideoCore to contain the GPU state. Also moved the GPU MemoryManager class to video_core since it makes more sense for it to be there. --- src/core/CMakeLists.txt | 2 - src/core/core.cpp | 2 + src/core/core.h | 7 ++ .../hle/service/nvdrv/devices/nvhost_as_gpu.cpp | 12 ++- src/core/hle/service/nvdrv/devices/nvhost_as_gpu.h | 5 +- src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp | 7 +- src/core/hle/service/nvdrv/devices/nvhost_gpu.h | 5 +- src/core/hle/service/nvdrv/memory_manager.cpp | 112 --------------------- src/core/hle/service/nvdrv/memory_manager.h | 48 --------- src/core/hle/service/nvdrv/nvdrv.cpp | 7 +- src/video_core/CMakeLists.txt | 3 + src/video_core/command_processor.cpp | 33 ++---- src/video_core/command_processor.h | 4 - src/video_core/engines/fermi_2d.cpp | 4 +- src/video_core/engines/fermi_2d.h | 10 +- src/video_core/engines/maxwell_3d.cpp | 4 +- src/video_core/engines/maxwell_3d.h | 10 +- src/video_core/engines/maxwell_compute.cpp | 4 +- src/video_core/engines/maxwell_compute.h | 10 +- src/video_core/gpu.h | 55 ++++++++++ src/video_core/memory_manager.cpp | 110 ++++++++++++++++++++ src/video_core/memory_manager.h | 49 +++++++++ 22 files changed, 276 insertions(+), 227 deletions(-) delete mode 100644 src/core/hle/service/nvdrv/memory_manager.cpp delete mode 100644 src/core/hle/service/nvdrv/memory_manager.h create mode 100644 src/video_core/gpu.h create mode 100644 src/video_core/memory_manager.cpp create mode 100644 src/video_core/memory_manager.h (limited to 'src') diff --git a/src/core/CMakeLists.txt b/src/core/CMakeLists.txt index a78d6d888..fc6cb67c7 100644 --- a/src/core/CMakeLists.txt +++ b/src/core/CMakeLists.txt @@ -139,8 +139,6 @@ add_library(core STATIC hle/service/nvdrv/devices/nvmap.h hle/service/nvdrv/interface.cpp hle/service/nvdrv/interface.h - hle/service/nvdrv/memory_manager.cpp - hle/service/nvdrv/memory_manager.h hle/service/nvdrv/nvdrv.cpp hle/service/nvdrv/nvdrv.h hle/service/nvdrv/nvmemp.cpp diff --git a/src/core/core.cpp b/src/core/core.cpp index dc21e4f04..613a98b4c 100644 --- a/src/core/core.cpp +++ b/src/core/core.cpp @@ -154,6 +154,8 @@ System::ResultStatus System::Init(EmuWindow* emu_window, u32 system_mode) { break; } + gpu_core = std::make_unique(); + telemetry_session = std::make_unique(); CoreTiming::Init(); diff --git a/src/core/core.h b/src/core/core.h index 06ab4c75f..f63cc47cc 100644 --- a/src/core/core.h +++ b/src/core/core.h @@ -11,6 +11,7 @@ #include "core/memory.h" #include "core/perf_stats.h" #include "core/telemetry_session.h" +#include "video_core/gpu.h" class EmuWindow; class ARM_Interface; @@ -102,6 +103,10 @@ public: return *cpu_core; } + Tegra::GPU& GPU() { + return *gpu_core; + } + PerfStats perf_stats; FrameLimiter frame_limiter; @@ -138,6 +143,8 @@ private: ///< ARM11 CPU core std::unique_ptr cpu_core; + std::unique_ptr gpu_core; + /// When true, signals that a reschedule should happen bool reschedule_pending{}; diff --git a/src/core/hle/service/nvdrv/devices/nvhost_as_gpu.cpp b/src/core/hle/service/nvdrv/devices/nvhost_as_gpu.cpp index cf3601f02..9832e1899 100644 --- a/src/core/hle/service/nvdrv/devices/nvhost_as_gpu.cpp +++ b/src/core/hle/service/nvdrv/devices/nvhost_as_gpu.cpp @@ -4,6 +4,7 @@ #include "common/assert.h" #include "common/logging/log.h" +#include "core/core.h" #include "core/hle/service/nvdrv/devices/nvhost_as_gpu.h" #include "core/hle/service/nvdrv/devices/nvmap.h" @@ -44,11 +45,12 @@ u32 nvhost_as_gpu::AllocateSpace(const std::vector& input, std::vector& LOG_DEBUG(Service_NVDRV, "called, pages=%x, page_size=%x, flags=%x", params.pages, params.page_size, params.flags); + auto& gpu = Core::System::GetInstance().GPU(); const u64 size{static_cast(params.pages) * static_cast(params.page_size)}; if (params.flags & 1) { - params.offset = memory_manager->AllocateSpace(params.offset, size, 1); + params.offset = gpu.memory_manager->AllocateSpace(params.offset, size, 1); } else { - params.offset = memory_manager->AllocateSpace(size, params.align); + params.offset = gpu.memory_manager->AllocateSpace(size, params.align); } std::memcpy(output.data(), ¶ms, output.size()); @@ -71,10 +73,12 @@ u32 nvhost_as_gpu::MapBufferEx(const std::vector& input, std::vector& ou auto object = nvmap_dev->GetObject(params.nvmap_handle); ASSERT(object); + auto& gpu = Core::System::GetInstance().GPU(); + if (params.flags & 1) { - params.offset = memory_manager->MapBufferEx(object->addr, params.offset, object->size); + params.offset = gpu.memory_manager->MapBufferEx(object->addr, params.offset, object->size); } else { - params.offset = memory_manager->MapBufferEx(object->addr, object->size); + params.offset = gpu.memory_manager->MapBufferEx(object->addr, object->size); } std::memcpy(output.data(), ¶ms, output.size()); diff --git a/src/core/hle/service/nvdrv/devices/nvhost_as_gpu.h b/src/core/hle/service/nvdrv/devices/nvhost_as_gpu.h index 301a8a79f..f8a60cce7 100644 --- a/src/core/hle/service/nvdrv/devices/nvhost_as_gpu.h +++ b/src/core/hle/service/nvdrv/devices/nvhost_as_gpu.h @@ -10,7 +10,6 @@ #include "common/common_types.h" #include "common/swap.h" #include "core/hle/service/nvdrv/devices/nvdevice.h" -#include "core/hle/service/nvdrv/memory_manager.h" namespace Service { namespace Nvidia { @@ -20,8 +19,7 @@ class nvmap; class nvhost_as_gpu final : public nvdevice { public: - nvhost_as_gpu(std::shared_ptr nvmap_dev, std::shared_ptr memory_manager) - : nvmap_dev(std::move(nvmap_dev)), memory_manager(std::move(memory_manager)) {} + nvhost_as_gpu(std::shared_ptr nvmap_dev) : nvmap_dev(std::move(nvmap_dev)) {} ~nvhost_as_gpu() override = default; u32 ioctl(Ioctl command, const std::vector& input, std::vector& output) override; @@ -100,7 +98,6 @@ private: u32 GetVARegions(const std::vector& input, std::vector& output); std::shared_ptr nvmap_dev; - std::shared_ptr memory_manager; }; } // namespace Devices diff --git a/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp b/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp index 1c3079889..0b2ebd466 100644 --- a/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp +++ b/src/core/hle/service/nvdrv/devices/nvhost_gpu.cpp @@ -5,8 +5,8 @@ #include #include "common/assert.h" #include "common/logging/log.h" +#include "core/core.h" #include "core/hle/service/nvdrv/devices/nvhost_gpu.h" -#include "video_core/command_processor.h" namespace Service { namespace Nvidia { @@ -131,9 +131,8 @@ u32 nvhost_gpu::SubmitGPFIFO(const std::vector& input, std::vector& outp std::memcpy(&entries[0], &input.data()[sizeof(IoctlSubmitGpfifo)], params.num_entries * sizeof(IoctlGpfifoEntry)); for (auto entry : entries) { - VAddr va_addr = memory_manager->PhysicalToVirtualAddress(entry.Address()); - Tegra::CommandProcessor::ProcessCommandList(va_addr, entry.sz); - // TODO(ogniK): Process these + VAddr va_addr = entry.Address(); + Core::System::GetInstance().GPU().ProcessCommandList(va_addr, entry.sz); } params.fence_out.id = 0; params.fence_out.value = 0; diff --git a/src/core/hle/service/nvdrv/devices/nvhost_gpu.h b/src/core/hle/service/nvdrv/devices/nvhost_gpu.h index 6f9b90b05..e7e9a0088 100644 --- a/src/core/hle/service/nvdrv/devices/nvhost_gpu.h +++ b/src/core/hle/service/nvdrv/devices/nvhost_gpu.h @@ -9,7 +9,6 @@ #include "common/common_types.h" #include "common/swap.h" #include "core/hle/service/nvdrv/devices/nvdevice.h" -#include "core/hle/service/nvdrv/memory_manager.h" namespace Service { namespace Nvidia { @@ -21,8 +20,7 @@ constexpr u32 NVGPU_IOCTL_CHANNEL_SUBMIT_GPFIFO(0x8); class nvhost_gpu final : public nvdevice { public: - nvhost_gpu(std::shared_ptr nvmap_dev, std::shared_ptr memory_manager) - : nvmap_dev(std::move(nvmap_dev)), memory_manager(std::move(memory_manager)) {} + nvhost_gpu(std::shared_ptr nvmap_dev) : nvmap_dev(std::move(nvmap_dev)) {} ~nvhost_gpu() override = default; u32 ioctl(Ioctl command, const std::vector& input, std::vector& output) override; @@ -139,7 +137,6 @@ private: u32 SubmitGPFIFO(const std::vector& input, std::vector& output); std::shared_ptr nvmap_dev; - std::shared_ptr memory_manager; }; } // namespace Devices diff --git a/src/core/hle/service/nvdrv/memory_manager.cpp b/src/core/hle/service/nvdrv/memory_manager.cpp deleted file mode 100644 index 55a8675d5..000000000 --- a/src/core/hle/service/nvdrv/memory_manager.cpp +++ /dev/null @@ -1,112 +0,0 @@ -// Copyright 2018 yuzu emulator team -// Licensed under GPLv2 or any later version -// Refer to the license.txt file included. - -#include "common/assert.h" -#include "core/hle/service/nvdrv/memory_manager.h" - -namespace Service { -namespace Nvidia { - -PAddr MemoryManager::AllocateSpace(u64 size, u64 align) { - boost::optional paddr = FindFreeBlock(size, align); - ASSERT(paddr); - - for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { - PageSlot(*paddr + offset) = static_cast(PageStatus::Allocated); - } - - return *paddr; -} - -PAddr MemoryManager::AllocateSpace(PAddr paddr, u64 size, u64 align) { - for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { - if (IsPageMapped(paddr + offset)) { - return AllocateSpace(size, align); - } - } - - for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { - PageSlot(paddr + offset) = static_cast(PageStatus::Allocated); - } - - return paddr; -} - -PAddr MemoryManager::MapBufferEx(VAddr vaddr, u64 size) { - vaddr &= ~Memory::PAGE_MASK; - - boost::optional paddr = FindFreeBlock(size); - ASSERT(paddr); - - for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { - PageSlot(*paddr + offset) = vaddr + offset; - } - - return *paddr; -} - -PAddr MemoryManager::MapBufferEx(VAddr vaddr, PAddr paddr, u64 size) { - vaddr &= ~Memory::PAGE_MASK; - paddr &= ~Memory::PAGE_MASK; - - for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { - if (PageSlot(paddr + offset) != static_cast(PageStatus::Allocated)) { - return MapBufferEx(vaddr, size); - } - } - - for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { - PageSlot(paddr + offset) = vaddr + offset; - } - - return paddr; -} - -boost::optional MemoryManager::FindFreeBlock(u64 size, u64 align) { - PAddr paddr{}; - u64 free_space{}; - align = (align + Memory::PAGE_MASK) & ~Memory::PAGE_MASK; - - while (paddr + free_space < MAX_ADDRESS) { - if (!IsPageMapped(paddr + free_space)) { - free_space += Memory::PAGE_SIZE; - if (free_space >= size) { - return paddr; - } - } else { - paddr += free_space + Memory::PAGE_SIZE; - free_space = 0; - const u64 remainder{paddr % align}; - if (!remainder) { - paddr = (paddr - remainder) + align; - } - } - } - - return {}; -} - -VAddr MemoryManager::PhysicalToVirtualAddress(PAddr paddr) { - VAddr base_addr = PageSlot(paddr); - ASSERT(base_addr != static_cast(PageStatus::Unmapped)); - return base_addr + (paddr & Memory::PAGE_MASK); -} - -bool MemoryManager::IsPageMapped(PAddr paddr) { - return PageSlot(paddr) != static_cast(PageStatus::Unmapped); -} - -VAddr& MemoryManager::PageSlot(PAddr paddr) { - auto& block = page_table[(paddr >> (Memory::PAGE_BITS + PAGE_TABLE_BITS)) & PAGE_TABLE_MASK]; - if (!block) { - block = std::make_unique(); - for (unsigned index = 0; index < PAGE_BLOCK_SIZE; index++) { - (*block)[index] = static_cast(PageStatus::Unmapped); - } - } - return (*block)[(paddr >> Memory::PAGE_BITS) & PAGE_BLOCK_MASK]; -} - -} // namespace Nvidia -} // namespace Service diff --git a/src/core/hle/service/nvdrv/memory_manager.h b/src/core/hle/service/nvdrv/memory_manager.h deleted file mode 100644 index 4ba1a3952..000000000 --- a/src/core/hle/service/nvdrv/memory_manager.h +++ /dev/null @@ -1,48 +0,0 @@ -// Copyright 2018 yuzu emulator team -// Licensed under GPLv2 or any later version -// Refer to the license.txt file included. - -#pragma once - -#include -#include -#include "common/common_types.h" -#include "core/memory.h" - -namespace Service { -namespace Nvidia { - -class MemoryManager final { -public: - MemoryManager() = default; - - PAddr AllocateSpace(u64 size, u64 align); - PAddr AllocateSpace(PAddr paddr, u64 size, u64 align); - PAddr MapBufferEx(VAddr vaddr, u64 size); - PAddr MapBufferEx(VAddr vaddr, PAddr paddr, u64 size); - VAddr PhysicalToVirtualAddress(PAddr paddr); - -private: - boost::optional FindFreeBlock(u64 size, u64 align = 1); - bool IsPageMapped(PAddr paddr); - VAddr& PageSlot(PAddr paddr); - - enum class PageStatus : u64 { - Unmapped = 0xFFFFFFFFFFFFFFFFULL, - Allocated = 0xFFFFFFFFFFFFFFFEULL, - }; - - static constexpr u64 MAX_ADDRESS{0x10000000000ULL}; - static constexpr u64 PAGE_TABLE_BITS{14}; - static constexpr u64 PAGE_TABLE_SIZE{1 << PAGE_TABLE_BITS}; - static constexpr u64 PAGE_TABLE_MASK{PAGE_TABLE_SIZE - 1}; - static constexpr u64 PAGE_BLOCK_BITS{14}; - static constexpr u64 PAGE_BLOCK_SIZE{1 << PAGE_BLOCK_BITS}; - static constexpr u64 PAGE_BLOCK_MASK{PAGE_BLOCK_SIZE - 1}; - - using PageBlock = std::array; - std::array, PAGE_TABLE_SIZE> page_table{}; -}; - -} // namespace Nvidia -} // namespace Service diff --git a/src/core/hle/service/nvdrv/nvdrv.cpp b/src/core/hle/service/nvdrv/nvdrv.cpp index 469d6d33a..ea00240e6 100644 --- a/src/core/hle/service/nvdrv/nvdrv.cpp +++ b/src/core/hle/service/nvdrv/nvdrv.cpp @@ -11,7 +11,6 @@ #include "core/hle/service/nvdrv/devices/nvhost_gpu.h" #include "core/hle/service/nvdrv/devices/nvmap.h" #include "core/hle/service/nvdrv/interface.h" -#include "core/hle/service/nvdrv/memory_manager.h" #include "core/hle/service/nvdrv/nvdrv.h" #include "core/hle/service/nvdrv/nvmemp.h" @@ -32,10 +31,8 @@ void InstallInterfaces(SM::ServiceManager& service_manager) { Module::Module() { auto nvmap_dev = std::make_shared(); - auto memory_manager = std::make_shared(); - devices["/dev/nvhost-as-gpu"] = - std::make_shared(nvmap_dev, memory_manager); - devices["/dev/nvhost-gpu"] = std::make_shared(nvmap_dev, memory_manager); + devices["/dev/nvhost-as-gpu"] = std::make_shared(nvmap_dev); + devices["/dev/nvhost-gpu"] = std::make_shared(nvmap_dev); devices["/dev/nvhost-ctrl-gpu"] = std::make_shared(); devices["/dev/nvmap"] = nvmap_dev; devices["/dev/nvdisp_disp0"] = std::make_shared(nvmap_dev); diff --git a/src/video_core/CMakeLists.txt b/src/video_core/CMakeLists.txt index 70728d2f6..ed87f8ff1 100644 --- a/src/video_core/CMakeLists.txt +++ b/src/video_core/CMakeLists.txt @@ -7,6 +7,9 @@ add_library(video_core STATIC engines/maxwell_3d.h engines/maxwell_compute.cpp engines/maxwell_compute.h + gpu.h + memory_manager.cpp + memory_manager.h renderer_base.cpp renderer_base.h renderer_opengl/gl_resource_manager.h diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp index e1df875e7..21d672085 100644 --- a/src/video_core/command_processor.cpp +++ b/src/video_core/command_processor.cpp @@ -16,30 +16,18 @@ #include "video_core/engines/fermi_2d.h" #include "video_core/engines/maxwell_3d.h" #include "video_core/engines/maxwell_compute.h" +#include "video_core/gpu.h" #include "video_core/renderer_base.h" #include "video_core/video_core.h" namespace Tegra { -namespace CommandProcessor { - enum class BufferMethods { BindObject = 0, CountBufferMethods = 0x100, }; -enum class EngineID { - FERMI_TWOD_A = 0x902D, // 2D Engine - MAXWELL_B = 0xB197, // 3D Engine - MAXWELL_COMPUTE_B = 0xB1C0, - KEPLER_INLINE_TO_MEMORY_B = 0xA140, - MAXWELL_DMA_COPY_A = 0xB0B5, -}; - -// Mapping of subchannels to their bound engine ids. -static std::unordered_map bound_engines; - -static void WriteReg(u32 method, u32 subchannel, u32 value) { +void GPU::WriteReg(u32 method, u32 subchannel, u32 value) { LOG_WARNING(HW_GPU, "Processing method %08X on subchannel %u value %08X", method, subchannel, value); @@ -63,22 +51,25 @@ static void WriteReg(u32 method, u32 subchannel, u32 value) { switch (engine) { case EngineID::FERMI_TWOD_A: - Engines::Fermi2D::WriteReg(method, value); + fermi_2d->WriteReg(method, value); break; case EngineID::MAXWELL_B: - Engines::Maxwell3D::WriteReg(method, value); + maxwell_3d->WriteReg(method, value); break; case EngineID::MAXWELL_COMPUTE_B: - Engines::MaxwellCompute::WriteReg(method, value); + maxwell_compute->WriteReg(method, value); break; default: UNIMPLEMENTED(); } } -void ProcessCommandList(VAddr address, u32 size) { - VAddr current_addr = address; - while (current_addr < address + size * sizeof(CommandHeader)) { +void GPU::ProcessCommandList(GPUVAddr address, u32 size) { + // TODO(Subv): PhysicalToVirtualAddress is a misnomer, it converts a GPU VAddr into an + // application VAddr. + const VAddr head_address = memory_manager->PhysicalToVirtualAddress(address); + VAddr current_addr = head_address; + while (current_addr < head_address + size * sizeof(CommandHeader)) { const CommandHeader header = {Memory::Read32(current_addr)}; current_addr += sizeof(u32); @@ -125,6 +116,4 @@ void ProcessCommandList(VAddr address, u32 size) { } } -} // namespace CommandProcessor - } // namespace Tegra diff --git a/src/video_core/command_processor.h b/src/video_core/command_processor.h index 90e64629e..b511bfcf7 100644 --- a/src/video_core/command_processor.h +++ b/src/video_core/command_processor.h @@ -10,8 +10,6 @@ namespace Tegra { -namespace CommandProcessor { - enum class SubmissionMode : u32 { IncreasingOld = 0, Increasing = 1, @@ -38,6 +36,4 @@ static_assert(sizeof(CommandHeader) == sizeof(u32), "CommandHeader has incorrect void ProcessCommandList(VAddr address, u32 size); -} // namespace CommandProcessor - } // namespace Tegra diff --git a/src/video_core/engines/fermi_2d.cpp b/src/video_core/engines/fermi_2d.cpp index 3d62c321f..7aab163dc 100644 --- a/src/video_core/engines/fermi_2d.cpp +++ b/src/video_core/engines/fermi_2d.cpp @@ -6,10 +6,8 @@ namespace Tegra { namespace Engines { -namespace Fermi2D { -void WriteReg(u32 method, u32 value) {} +void Fermi2D::WriteReg(u32 method, u32 value) {} -} // namespace Fermi2D } // namespace Engines } // namespace Tegra diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h index 6f3f5dfbc..8967ddede 100644 --- a/src/video_core/engines/fermi_2d.h +++ b/src/video_core/engines/fermi_2d.h @@ -8,11 +8,15 @@ namespace Tegra { namespace Engines { -namespace Fermi2D { -void WriteReg(u32 method, u32 value); +class Fermi2D final { +public: + Fermi2D() = default; + ~Fermi2D() = default; -} // namespace Fermi2D + /// Write the value to the register identified by method. + void WriteReg(u32 method, u32 value); +}; } // namespace Engines } // namespace Tegra diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp index c2697c960..ccdb310f0 100644 --- a/src/video_core/engines/maxwell_3d.cpp +++ b/src/video_core/engines/maxwell_3d.cpp @@ -6,10 +6,8 @@ namespace Tegra { namespace Engines { -namespace Maxwell3D { -void WriteReg(u32 method, u32 value) {} +void Maxwell3D::WriteReg(u32 method, u32 value) {} -} // namespace Maxwell3D } // namespace Engines } // namespace Tegra diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h index 6957fb721..0f4ae1328 100644 --- a/src/video_core/engines/maxwell_3d.h +++ b/src/video_core/engines/maxwell_3d.h @@ -8,11 +8,15 @@ namespace Tegra { namespace Engines { -namespace Maxwell3D { -void WriteReg(u32 method, u32 value); +class Maxwell3D final { +public: + Maxwell3D() = default; + ~Maxwell3D() = default; -} // namespace Maxwell3D + /// Write the value to the register identified by method. + void WriteReg(u32 method, u32 value); +}; } // namespace Engines } // namespace Tegra diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp index c2134d63b..e4e5f9e5e 100644 --- a/src/video_core/engines/maxwell_compute.cpp +++ b/src/video_core/engines/maxwell_compute.cpp @@ -6,10 +6,8 @@ namespace Tegra { namespace Engines { -namespace MaxwellCompute { -void WriteReg(u32 method, u32 value) {} +void MaxwellCompute::WriteReg(u32 method, u32 value) {} -} // namespace MaxwellCompute } // namespace Engines } // namespace Tegra diff --git a/src/video_core/engines/maxwell_compute.h b/src/video_core/engines/maxwell_compute.h index dc9a13593..7262e1bcb 100644 --- a/src/video_core/engines/maxwell_compute.h +++ b/src/video_core/engines/maxwell_compute.h @@ -8,11 +8,15 @@ namespace Tegra { namespace Engines { -namespace MaxwellCompute { -void WriteReg(u32 method, u32 value); +class MaxwellCompute final { +public: + MaxwellCompute() = default; + ~MaxwellCompute() = default; -} // namespace MaxwellCompute + /// Write the value to the register identified by method. + void WriteReg(u32 method, u32 value); +}; } // namespace Engines } // namespace Tegra diff --git a/src/video_core/gpu.h b/src/video_core/gpu.h new file mode 100644 index 000000000..a961f3fd4 --- /dev/null +++ b/src/video_core/gpu.h @@ -0,0 +1,55 @@ +// Copyright 2018 yuzu Emulator Project +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#pragma once + +#include +#include +#include "common/common_types.h" +#include "video_core/engines/fermi_2d.h" +#include "video_core/engines/maxwell_3d.h" +#include "video_core/engines/maxwell_compute.h" +#include "video_core/memory_manager.h" + +namespace Tegra { + +enum class EngineID { + FERMI_TWOD_A = 0x902D, // 2D Engine + MAXWELL_B = 0xB197, // 3D Engine + MAXWELL_COMPUTE_B = 0xB1C0, + KEPLER_INLINE_TO_MEMORY_B = 0xA140, + MAXWELL_DMA_COPY_A = 0xB0B5, +}; + +class GPU final { +public: + GPU() { + memory_manager = std::make_unique(); + maxwell_3d = std::make_unique(); + fermi_2d = std::make_unique(); + maxwell_compute = std::make_unique(); + } + ~GPU() = default; + + /// Processes a command list stored at the specified address in GPU memory. + void ProcessCommandList(GPUVAddr address, u32 size); + + std::unique_ptr memory_manager; + +private: + /// Writes a single register in the engine bound to the specified subchannel + void WriteReg(u32 method, u32 subchannel, u32 value); + + /// Mapping of command subchannels to their bound engine ids. + std::unordered_map bound_engines; + + /// 3D engine + std::unique_ptr maxwell_3d; + /// 2D engine + std::unique_ptr fermi_2d; + /// Compute engine + std::unique_ptr maxwell_compute; +}; + +} // namespace Tegra diff --git a/src/video_core/memory_manager.cpp b/src/video_core/memory_manager.cpp new file mode 100644 index 000000000..2789a4ca1 --- /dev/null +++ b/src/video_core/memory_manager.cpp @@ -0,0 +1,110 @@ +// Copyright 2018 yuzu emulator team +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#include "common/assert.h" +#include "video_core/memory_manager.h" + +namespace Tegra { + +PAddr MemoryManager::AllocateSpace(u64 size, u64 align) { + boost::optional paddr = FindFreeBlock(size, align); + ASSERT(paddr); + + for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { + PageSlot(*paddr + offset) = static_cast(PageStatus::Allocated); + } + + return *paddr; +} + +PAddr MemoryManager::AllocateSpace(PAddr paddr, u64 size, u64 align) { + for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { + if (IsPageMapped(paddr + offset)) { + return AllocateSpace(size, align); + } + } + + for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { + PageSlot(paddr + offset) = static_cast(PageStatus::Allocated); + } + + return paddr; +} + +PAddr MemoryManager::MapBufferEx(VAddr vaddr, u64 size) { + vaddr &= ~Memory::PAGE_MASK; + + boost::optional paddr = FindFreeBlock(size); + ASSERT(paddr); + + for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { + PageSlot(*paddr + offset) = vaddr + offset; + } + + return *paddr; +} + +PAddr MemoryManager::MapBufferEx(VAddr vaddr, PAddr paddr, u64 size) { + vaddr &= ~Memory::PAGE_MASK; + paddr &= ~Memory::PAGE_MASK; + + for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { + if (PageSlot(paddr + offset) != static_cast(PageStatus::Allocated)) { + return MapBufferEx(vaddr, size); + } + } + + for (u64 offset = 0; offset < size; offset += Memory::PAGE_SIZE) { + PageSlot(paddr + offset) = vaddr + offset; + } + + return paddr; +} + +boost::optional MemoryManager::FindFreeBlock(u64 size, u64 align) { + PAddr paddr{}; + u64 free_space{}; + align = (align + Memory::PAGE_MASK) & ~Memory::PAGE_MASK; + + while (paddr + free_space < MAX_ADDRESS) { + if (!IsPageMapped(paddr + free_space)) { + free_space += Memory::PAGE_SIZE; + if (free_space >= size) { + return paddr; + } + } else { + paddr += free_space + Memory::PAGE_SIZE; + free_space = 0; + const u64 remainder{paddr % align}; + if (!remainder) { + paddr = (paddr - remainder) + align; + } + } + } + + return {}; +} + +VAddr MemoryManager::PhysicalToVirtualAddress(PAddr paddr) { + VAddr base_addr = PageSlot(paddr); + ASSERT(base_addr != static_cast(PageStatus::Unmapped)); + return base_addr + (paddr & Memory::PAGE_MASK); +} + +bool MemoryManager::IsPageMapped(PAddr paddr) { + return PageSlot(paddr) != static_cast(PageStatus::Unmapped); +} + +VAddr& MemoryManager::PageSlot(PAddr paddr) { + auto& block = page_table[(paddr >> (Memory::PAGE_BITS + PAGE_TABLE_BITS)) & PAGE_TABLE_MASK]; + if (!block) { + block = std::make_unique(); + for (unsigned index = 0; index < PAGE_BLOCK_SIZE; index++) { + (*block)[index] = static_cast(PageStatus::Unmapped); + } + } + return (*block)[(paddr >> Memory::PAGE_BITS) & PAGE_BLOCK_MASK]; +} + +} // namespace Tegra diff --git a/src/video_core/memory_manager.h b/src/video_core/memory_manager.h new file mode 100644 index 000000000..47da7acd6 --- /dev/null +++ b/src/video_core/memory_manager.h @@ -0,0 +1,49 @@ +// Copyright 2018 yuzu emulator team +// Licensed under GPLv2 or any later version +// Refer to the license.txt file included. + +#pragma once + +#include +#include +#include "common/common_types.h" +#include "core/memory.h" + +namespace Tegra { + +/// Virtual addresses in the GPU's memory map are 64 bit. +using GPUVAddr = u64; + +class MemoryManager final { +public: + MemoryManager() = default; + + PAddr AllocateSpace(u64 size, u64 align); + PAddr AllocateSpace(PAddr paddr, u64 size, u64 align); + PAddr MapBufferEx(VAddr vaddr, u64 size); + PAddr MapBufferEx(VAddr vaddr, PAddr paddr, u64 size); + VAddr PhysicalToVirtualAddress(PAddr paddr); + +private: + boost::optional FindFreeBlock(u64 size, u64 align = 1); + bool IsPageMapped(PAddr paddr); + VAddr& PageSlot(PAddr paddr); + + enum class PageStatus : u64 { + Unmapped = 0xFFFFFFFFFFFFFFFFULL, + Allocated = 0xFFFFFFFFFFFFFFFEULL, + }; + + static constexpr u64 MAX_ADDRESS{0x10000000000ULL}; + static constexpr u64 PAGE_TABLE_BITS{14}; + static constexpr u64 PAGE_TABLE_SIZE{1 << PAGE_TABLE_BITS}; + static constexpr u64 PAGE_TABLE_MASK{PAGE_TABLE_SIZE - 1}; + static constexpr u64 PAGE_BLOCK_BITS{14}; + static constexpr u64 PAGE_BLOCK_SIZE{1 << PAGE_BLOCK_BITS}; + static constexpr u64 PAGE_BLOCK_MASK{PAGE_BLOCK_SIZE - 1}; + + using PageBlock = std::array; + std::array, PAGE_TABLE_SIZE> page_table{}; +}; + +} // namespace Tegra -- cgit v1.2.3