From 18a766b3622baa40596490dbd4912f94e9980a76 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Mon, 22 Feb 2021 02:45:50 -0300
Subject: shader: Fix MOV(reg), add SHL variants and emit neg and abs
 instructions

---
 src/shader_recompiler/backend/spirv/emit_spirv.h                  | 4 ++--
 src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp        | 8 ++++----
 .../frontend/maxwell/translate/impl/integer_shift_left.cpp        | 8 ++++----
 .../frontend/maxwell/translate/impl/move_register.cpp             | 2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

(limited to 'src')

diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index cec80c13e..1b9be445e 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -181,8 +181,8 @@ void EmitIAdd64(EmitContext& ctx);
 Id EmitISub32(EmitContext& ctx, Id a, Id b);
 void EmitISub64(EmitContext& ctx);
 Id EmitIMul32(EmitContext& ctx, Id a, Id b);
-void EmitINeg32(EmitContext& ctx);
-void EmitIAbs32(EmitContext& ctx);
+Id EmitINeg32(EmitContext& ctx, Id value);
+Id EmitIAbs32(EmitContext& ctx, Id value);
 Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
 void EmitShiftRightLogical32(EmitContext& ctx);
 void EmitShiftRightArithmetic32(EmitContext& ctx);
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 4c0b5990d..329dcb351 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -58,12 +58,12 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b) {
     return ctx.OpIMul(ctx.U32[1], a, b);
 }
 
-void EmitINeg32(EmitContext&) {
-    throw NotImplementedException("SPIR-V Instruction");
+Id EmitINeg32(EmitContext& ctx, Id value) {
+    return ctx.OpSNegate(ctx.U32[1], value);
 }
 
-void EmitIAbs32(EmitContext&) {
-    throw NotImplementedException("SPIR-V Instruction");
+Id EmitIAbs32(EmitContext& ctx, Id value) {
+    return ctx.OpSAbs(ctx.U32[1], value);
 }
 
 Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_left.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_left.cpp
index b752785d4..d8a5158b5 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_left.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/integer_shift_left.cpp
@@ -56,12 +56,12 @@ void SHL(TranslatorVisitor& v, u64 insn, const IR::U32& unsafe_shift) {
 }
 } // Anonymous namespace
 
-void TranslatorVisitor::SHL_reg(u64) {
-    throw NotImplementedException("SHL_reg");
+void TranslatorVisitor::SHL_reg(u64 insn) {
+    SHL(*this, insn, GetReg20(insn));
 }
 
-void TranslatorVisitor::SHL_cbuf(u64) {
-    throw NotImplementedException("SHL_cbuf");
+void TranslatorVisitor::SHL_cbuf(u64 insn) {
+    SHL(*this, insn, GetCbuf(insn));
 }
 
 void TranslatorVisitor::SHL_imm(u64 insn) {
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
index c3c4b9abd..6bb08db8a 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register.cpp
@@ -26,7 +26,7 @@ void MOV(TranslatorVisitor& v, u64 insn, const IR::U32& src, bool is_mov32i = fa
 } // Anonymous namespace
 
 void TranslatorVisitor::MOV_reg(u64 insn) {
-    MOV(*this, insn, GetReg8(insn));
+    MOV(*this, insn, GetReg20(insn));
 }
 
 void TranslatorVisitor::MOV_cbuf(u64 insn) {
-- 
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