From 5a9df3c6753e66519acaa13685abb89231e45ade Mon Sep 17 00:00:00 2001 From: Subv Date: Tue, 3 Jul 2018 22:32:59 -0500 Subject: GPU: Only configure the used framebuffers during clear. Don't try to configure the color buffer if it is not being cleared, it may not be completely valid at this point. --- src/video_core/renderer_opengl/gl_rasterizer_cache.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) (limited to 'src/video_core/renderer_opengl/gl_rasterizer_cache.h') diff --git a/src/video_core/renderer_opengl/gl_rasterizer_cache.h b/src/video_core/renderer_opengl/gl_rasterizer_cache.h index 7aaf371bd..8005a81b8 100644 --- a/src/video_core/renderer_opengl/gl_rasterizer_cache.h +++ b/src/video_core/renderer_opengl/gl_rasterizer_cache.h @@ -326,13 +326,18 @@ struct SurfaceParams { return addr <= (region_addr + region_size) && region_addr <= (addr + size_in_bytes); } - /// Creates SurfaceParams from a texture configation + /// Creates SurfaceParams from a texture configuration static SurfaceParams CreateForTexture(const Tegra::Texture::FullTextureInfo& config); - /// Creates SurfaceParams from a framebuffer configation + /// Creates SurfaceParams from a framebuffer configuration static SurfaceParams CreateForFramebuffer( const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& config); + /// Creates SurfaceParams for a depth buffer configuration + static SurfaceParams CreateForDepthBuffer( + const Tegra::Engines::Maxwell3D::Regs::RenderTargetConfig& config, + Tegra::GPUVAddr zeta_address, Tegra::DepthFormat format); + Tegra::GPUVAddr addr; bool is_tiled; u32 block_height; -- cgit v1.2.3