From 752659aef3f16111981a097989dd7a5ddecff316 Mon Sep 17 00:00:00 2001
From: Kelebek1 <eeeedddccc@hotmail.co.uk>
Date: Fri, 12 Aug 2022 10:58:09 +0100
Subject: Update 3D regs

---
 src/video_core/gpu.h | 50 +++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 41 insertions(+), 9 deletions(-)

(limited to 'src/video_core/gpu.h')

diff --git a/src/video_core/gpu.h b/src/video_core/gpu.h
index 0a4a8b14f..d0709dc69 100644
--- a/src/video_core/gpu.h
+++ b/src/video_core/gpu.h
@@ -24,11 +24,15 @@ namespace Tegra {
 class DmaPusher;
 struct CommandList;
 
+// TODO: Implement the commented ones
 enum class RenderTargetFormat : u32 {
     NONE = 0x0,
     R32B32G32A32_FLOAT = 0xC0,
     R32G32B32A32_SINT = 0xC1,
     R32G32B32A32_UINT = 0xC2,
+    // R32G32B32X32_FLOAT = 0xC3,
+    // R32G32B32X32_SINT = 0xC4,
+    // R32G32B32X32_UINT = 0xC5,
     R16G16B16A16_UNORM = 0xC6,
     R16G16B16A16_SNORM = 0xC7,
     R16G16B16A16_SINT = 0xC8,
@@ -38,8 +42,8 @@ enum class RenderTargetFormat : u32 {
     R32G32_SINT = 0xCC,
     R32G32_UINT = 0xCD,
     R16G16B16X16_FLOAT = 0xCE,
-    B8G8R8A8_UNORM = 0xCF,
-    B8G8R8A8_SRGB = 0xD0,
+    A8R8G8B8_UNORM = 0xCF,
+    A8R8G8B8_SRGB = 0xD0,
     A2B10G10R10_UNORM = 0xD1,
     A2B10G10R10_UINT = 0xD2,
     A8B8G8R8_UNORM = 0xD5,
@@ -52,10 +56,13 @@ enum class RenderTargetFormat : u32 {
     R16G16_SINT = 0xDC,
     R16G16_UINT = 0xDD,
     R16G16_FLOAT = 0xDE,
+    // A2R10G10B10_UNORM = 0xDF,
     B10G11R11_FLOAT = 0xE0,
     R32_SINT = 0xE3,
     R32_UINT = 0xE4,
     R32_FLOAT = 0xE5,
+    // X8R8G8B8_UNORM = 0xE6,
+    // X8R8G8B8_SRGB = 0xE7,
     R5G6B5_UNORM = 0xE8,
     A1R5G5B5_UNORM = 0xE9,
     R8G8_UNORM = 0xEA,
@@ -71,17 +78,42 @@ enum class RenderTargetFormat : u32 {
     R8_SNORM = 0xF4,
     R8_SINT = 0xF5,
     R8_UINT = 0xF6,
+
+    /*
+    A8_UNORM = 0xF7,
+    X1R5G5B5_UNORM = 0xF8,
+    X8B8G8R8_UNORM = 0xF9,
+    X8B8G8R8_SRGB = 0xFA,
+    Z1R5G5B5_UNORM = 0xFB,
+    O1R5G5B5_UNORM = 0xFC,
+    Z8R8G8B8_UNORM = 0xFD,
+    O8R8G8B8_UNORM = 0xFE,
+    R32_UNORM = 0xFF,
+    A16_UNORM = 0x40,
+    A16_FLOAT = 0x41,
+    A32_FLOAT = 0x42,
+    A8R8_UNORM = 0x43,
+    R16A16_UNORM = 0x44,
+    R16A16_FLOAT = 0x45,
+    R32A32_FLOAT = 0x46,
+    B8G8R8A8_UNORM = 0x47,
+    */
 };
 
 enum class DepthFormat : u32 {
-    D32_FLOAT = 0xA,
-    D16_UNORM = 0x13,
-    S8_UINT_Z24_UNORM = 0x14,
-    D24X8_UNORM = 0x15,
-    D24S8_UNORM = 0x16,
+    Z32_FLOAT = 0xA,
+    Z16_UNORM = 0x13,
+    Z24_UNORM_S8_UINT = 0x14,
+    X8Z24_UNORM = 0x15,
+    S8Z24_UNORM = 0x16,
     S8_UINT = 0x17,
-    D24C8_UNORM = 0x18,
-    D32_FLOAT_S8X24_UINT = 0x19,
+    V8Z24_UNORM = 0x18,
+    Z32_FLOAT_X24S8_UINT = 0x19,
+    /*
+    X8Z24_UNORM_X16V8S8_UINT = 0x1D,
+    Z32_FLOAT_X16V8X8_UINT = 0x1E,
+    Z32_FLOAT_X16V8S8_UINT = 0x1F,
+    */
 };
 
 namespace Engines {
-- 
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