From 9bb3e008c9f4bbdd35c095b506c3a3312d17e383 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Tue, 18 May 2021 02:04:22 -0300
Subject: shader: Read branch conditions from an instruction

Fixes the identity removal pass.
---
 src/shader_recompiler/frontend/ir/ir_emitter.cpp                 | 8 ++++++--
 src/shader_recompiler/frontend/ir/ir_emitter.h                   | 4 +++-
 src/shader_recompiler/frontend/ir/microinstruction.cpp           | 3 ++-
 src/shader_recompiler/frontend/ir/opcodes.inc                    | 3 ++-
 .../frontend/maxwell/structured_control_flow.cpp                 | 9 +++------
 5 files changed, 16 insertions(+), 11 deletions(-)

(limited to 'src/shader_recompiler/frontend')

diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index 94bdbe39c..e9fd41237 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -61,8 +61,12 @@ F64 IREmitter::Imm64(f64 value) const {
     return F64{Value{value}};
 }
 
-void IREmitter::DummyReference(const Value& value) {
-    Inst(Opcode::DummyReference, value);
+U1 IREmitter::ConditionRef(const U1& value) {
+    return Inst<U1>(Opcode::ConditionRef, value);
+}
+
+void IREmitter::Reference(const Value& value) {
+    Inst(Opcode::Reference, value);
 }
 
 void IREmitter::PhiMove(IR::Inst& phi, const Value& value) {
diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.h b/src/shader_recompiler/frontend/ir/ir_emitter.h
index 4ae69b788..bb3500c54 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.h
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.h
@@ -32,7 +32,9 @@ public:
     [[nodiscard]] U64 Imm64(s64 value) const;
     [[nodiscard]] F64 Imm64(f64 value) const;
 
-    void DummyReference(const Value& value);
+    U1 ConditionRef(const U1& value);
+    void Reference(const Value& value);
+
     void PhiMove(IR::Inst& phi, const Value& value);
 
     void Prologue();
diff --git a/src/shader_recompiler/frontend/ir/microinstruction.cpp b/src/shader_recompiler/frontend/ir/microinstruction.cpp
index 267aebc61..3dfa5a880 100644
--- a/src/shader_recompiler/frontend/ir/microinstruction.cpp
+++ b/src/shader_recompiler/frontend/ir/microinstruction.cpp
@@ -56,7 +56,8 @@ Inst::~Inst() {
 
 bool Inst::MayHaveSideEffects() const noexcept {
     switch (op) {
-    case Opcode::DummyReference:
+    case Opcode::ConditionRef:
+    case Opcode::Reference:
     case Opcode::PhiMove:
     case Opcode::Prologue:
     case Opcode::Epilogue:
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc
index 6196b867d..8a8d0d759 100644
--- a/src/shader_recompiler/frontend/ir/opcodes.inc
+++ b/src/shader_recompiler/frontend/ir/opcodes.inc
@@ -6,7 +6,8 @@
 OPCODE(Phi,                                                 Opaque,                                                                                         )
 OPCODE(Identity,                                            Opaque,         Opaque,                                                                         )
 OPCODE(Void,                                                Void,                                                                                           )
-OPCODE(DummyReference,                                      Void,           Opaque,                                                                         )
+OPCODE(ConditionRef,                                        U1,             U1,                                                                             )
+OPCODE(Reference,                                           Void,           Opaque,                                                                         )
 OPCODE(PhiMove,                                             Void,           Opaque,         Opaque,                                                         )
 
 // Special operations
diff --git a/src/shader_recompiler/frontend/maxwell/structured_control_flow.cpp b/src/shader_recompiler/frontend/maxwell/structured_control_flow.cpp
index 83554a953..ebe5c2654 100644
--- a/src/shader_recompiler/frontend/maxwell/structured_control_flow.cpp
+++ b/src/shader_recompiler/frontend/maxwell/structured_control_flow.cpp
@@ -703,8 +703,7 @@ private:
 
                 // Implement if header block
                 IR::IREmitter ir{*current_block};
-                const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
-                ir.DummyReference(cond);
+                const IR::U1 cond{ir.ConditionRef(VisitExpr(ir, *stmt.cond))};
 
                 const size_t if_node_index{syntax_list.size()};
                 syntax_list.emplace_back();
@@ -754,8 +753,7 @@ private:
 
                 // The continue block is located at the end of the loop
                 IR::IREmitter ir{*continue_block};
-                const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
-                ir.DummyReference(cond);
+                const IR::U1 cond{ir.ConditionRef(VisitExpr(ir, *stmt.cond))};
 
                 IR::Block* const body_block{syntax_list.at(body_block_index).data.block};
                 loop_header_block->AddBranch(body_block);
@@ -791,8 +789,7 @@ private:
                 IR::Block* const skip_block{MergeBlock(parent, stmt)};
 
                 IR::IREmitter ir{*current_block};
-                const IR::U1 cond{VisitExpr(ir, *stmt.cond)};
-                ir.DummyReference(cond);
+                const IR::U1 cond{ir.ConditionRef(VisitExpr(ir, *stmt.cond))};
                 current_block->AddBranch(break_block);
                 current_block->AddBranch(skip_block);
                 current_block = skip_block;
-- 
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