From 7d6ba5b9840a4ba00a9b0f207c1c119d60dcf8b7 Mon Sep 17 00:00:00 2001
From: ameerj <52414509+ameerj@users.noreply.github.com>
Date: Sun, 7 Mar 2021 22:01:22 -0500
Subject: shader: Implement R2P

---
 src/shader_recompiler/frontend/ir/ir_emitter.cpp   |  2 +
 src/shader_recompiler/frontend/ir/opcodes.inc      |  1 +
 .../translate/impl/move_register_to_predicate.cpp  | 71 ++++++++++++++++++++++
 .../maxwell/translate/impl/not_implemented.cpp     | 12 ----
 4 files changed, 74 insertions(+), 12 deletions(-)
 create mode 100644 src/shader_recompiler/frontend/maxwell/translate/impl/move_register_to_predicate.cpp

(limited to 'src/shader_recompiler/frontend')

diff --git a/src/shader_recompiler/frontend/ir/ir_emitter.cpp b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
index 1659b7f3b..f38b46bac 100644
--- a/src/shader_recompiler/frontend/ir/ir_emitter.cpp
+++ b/src/shader_recompiler/frontend/ir/ir_emitter.cpp
@@ -412,6 +412,8 @@ Value IREmitter::Select(const U1& condition, const Value& true_value, const Valu
         throw InvalidArgument("Mismatching types {} and {}", true_value.Type(), false_value.Type());
     }
     switch (true_value.Type()) {
+    case Type::U1:
+        return Inst(Opcode::SelectU1, condition, true_value, false_value);
     case Type::U8:
         return Inst(Opcode::SelectU8, condition, true_value, false_value);
     case Type::U16:
diff --git a/src/shader_recompiler/frontend/ir/opcodes.inc b/src/shader_recompiler/frontend/ir/opcodes.inc
index 75f09ebfc..c4e72c84d 100644
--- a/src/shader_recompiler/frontend/ir/opcodes.inc
+++ b/src/shader_recompiler/frontend/ir/opcodes.inc
@@ -115,6 +115,7 @@ OPCODE(CompositeInsertF64x3,                                F64x3,          F64x
 OPCODE(CompositeInsertF64x4,                                F64x4,          F64x4,          F64,            U32,                            )
 
 // Select operations
+OPCODE(SelectU1,                                            U1,             U1,             U1,             U1,                             )
 OPCODE(SelectU8,                                            U8,             U1,             U8,             U8,                             )
 OPCODE(SelectU16,                                           U16,            U1,             U16,            U16,                            )
 OPCODE(SelectU32,                                           U32,            U1,             U32,            U32,                            )
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/move_register_to_predicate.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register_to_predicate.cpp
new file mode 100644
index 000000000..eda5f177b
--- /dev/null
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/move_register_to_predicate.cpp
@@ -0,0 +1,71 @@
+// Copyright 2021 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "common/bit_field.h"
+#include "shader_recompiler/exception.h"
+#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
+
+namespace Shader::Maxwell {
+namespace {
+enum class Mode : u64 {
+    PR,
+    CC,
+};
+
+void SetFlag(IR::IREmitter& ir, const IR::U1& inv_mask_bit, const IR::U1& src_bit, u32 index) {
+    switch (index) {
+    case 0:
+        return ir.SetZFlag(IR::U1{ir.Select(inv_mask_bit, ir.GetZFlag(), src_bit)});
+    case 1:
+        return ir.SetSFlag(IR::U1{ir.Select(inv_mask_bit, ir.GetSFlag(), src_bit)});
+    case 2:
+        return ir.SetCFlag(IR::U1{ir.Select(inv_mask_bit, ir.GetCFlag(), src_bit)});
+    case 3:
+        return ir.SetOFlag(IR::U1{ir.Select(inv_mask_bit, ir.GetOFlag(), src_bit)});
+    default:
+        throw LogicError("Unreachable R2P index");
+    }
+}
+
+void R2P(TranslatorVisitor& v, u64 insn, const IR::U32& mask) {
+    union {
+        u64 raw;
+        BitField<8, 8, IR::Reg> src_reg;
+        BitField<40, 1, Mode> mode;
+        BitField<41, 2, u64> byte_selector;
+    } const r2p{insn};
+    const IR::U32 src{v.X(r2p.src_reg)};
+    const IR::U32 count{v.ir.Imm32(1)};
+    const bool pr_mode{r2p.mode == Mode::PR};
+    const u32 num_items{pr_mode ? 7U : 4U};
+    const u32 offset_base{static_cast<u32>(r2p.byte_selector) * 8};
+    for (u32 index = 0; index < num_items; ++index) {
+        const IR::U32 offset{v.ir.Imm32(offset_base + index)};
+        const IR::U1 src_zero{v.ir.GetZeroFromOp(v.ir.BitFieldExtract(src, offset, count, false))};
+        const IR::U1 src_bit{v.ir.LogicalNot(src_zero)};
+        const IR::U32 mask_bfe{v.ir.BitFieldExtract(mask, v.ir.Imm32(index), count, false)};
+        const IR::U1 inv_mask_bit{v.ir.GetZeroFromOp(mask_bfe)};
+        if (pr_mode) {
+            const IR::Pred pred{index};
+            v.ir.SetPred(pred, IR::U1{v.ir.Select(inv_mask_bit, v.ir.GetPred(pred), src_bit)});
+        } else {
+            SetFlag(v.ir, inv_mask_bit, src_bit, index);
+        }
+    }
+}
+} // Anonymous namespace
+
+void TranslatorVisitor::R2P_reg(u64 insn) {
+    R2P(*this, insn, GetReg20(insn));
+}
+
+void TranslatorVisitor::R2P_cbuf(u64 insn) {
+    R2P(*this, insn, GetCbuf(insn));
+}
+
+void TranslatorVisitor::R2P_imm(u64 insn) {
+    R2P(*this, insn, GetImm20(insn));
+}
+
+} // namespace Shader::Maxwell
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
index 2ab90d1bf..fc6030e04 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
@@ -513,18 +513,6 @@ void TranslatorVisitor::R2B(u64) {
     ThrowNotImplemented(Opcode::R2B);
 }
 
-void TranslatorVisitor::R2P_reg(u64) {
-    ThrowNotImplemented(Opcode::R2P_reg);
-}
-
-void TranslatorVisitor::R2P_cbuf(u64) {
-    ThrowNotImplemented(Opcode::R2P_cbuf);
-}
-
-void TranslatorVisitor::R2P_imm(u64) {
-    ThrowNotImplemented(Opcode::R2P_imm);
-}
-
 void TranslatorVisitor::RAM(u64) {
     ThrowNotImplemented(Opcode::RAM);
 }
-- 
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