From 95815a3883d708f71db5119f42243e183f32f9a2 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Fri, 16 Apr 2021 17:22:59 -0300
Subject: shader: Implement PIXLD.MY_INDEX

---
 .../maxwell/translate/impl/not_implemented.cpp     |  4 --
 .../frontend/maxwell/translate/impl/pixel_load.cpp | 46 ++++++++++++++++++++++
 2 files changed, 46 insertions(+), 4 deletions(-)
 create mode 100644 src/shader_recompiler/frontend/maxwell/translate/impl/pixel_load.cpp

(limited to 'src/shader_recompiler/frontend/maxwell')

diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
index a45d1e4be..a4f99bbbe 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/not_implemented.cpp
@@ -181,10 +181,6 @@ void TranslatorVisitor::PEXIT(u64) {
     ThrowNotImplemented(Opcode::PEXIT);
 }
 
-void TranslatorVisitor::PIXLD(u64) {
-    ThrowNotImplemented(Opcode::PIXLD);
-}
-
 void TranslatorVisitor::PLONGJMP(u64) {
     ThrowNotImplemented(Opcode::PLONGJMP);
 }
diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/pixel_load.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/pixel_load.cpp
new file mode 100644
index 000000000..b4767afb5
--- /dev/null
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/pixel_load.cpp
@@ -0,0 +1,46 @@
+// Copyright 2021 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#include "common/bit_field.h"
+#include "common/common_types.h"
+#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
+
+namespace Shader::Maxwell {
+namespace {
+enum class Mode : u64 {
+    Default,
+    CovMask,
+    Covered,
+    Offset,
+    CentroidOffset,
+    MyIndex,
+};
+} // Anonymous namespace
+
+void TranslatorVisitor::PIXLD(u64 insn) {
+    union {
+        u64 raw;
+        BitField<31, 3, Mode> mode;
+        BitField<0, 8, IR::Reg> dest_reg;
+        BitField<8, 8, IR::Reg> addr_reg;
+        BitField<20, 8, s64> addr_offset;
+        BitField<45, 3, IR::Pred> dest_pred;
+    } const pixld{insn};
+
+    if (pixld.dest_pred != IR::Pred::PT) {
+        throw NotImplementedException("Destination predicate");
+    }
+    if (pixld.addr_reg != IR::Reg::RZ || pixld.addr_offset != 0) {
+        throw NotImplementedException("Non-zero source register");
+    }
+    switch (pixld.mode) {
+    case Mode::MyIndex:
+        X(pixld.dest_reg, ir.SampleId());
+        break;
+    default:
+        throw NotImplementedException("Mode {}", pixld.mode.Value());
+    }
+}
+
+} // namespace Shader::Maxwell
-- 
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