From 2ed80f6b1e85823d7a13dfbb119545a0a0ec7427 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Sun, 11 Apr 2021 19:16:47 -0300
Subject: shader: Implement LOP CC

---
 .../frontend/maxwell/translate/impl/logic_operation.cpp    | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

(limited to 'src/shader_recompiler/frontend/maxwell/translate/impl/logic_operation.cpp')

diff --git a/src/shader_recompiler/frontend/maxwell/translate/impl/logic_operation.cpp b/src/shader_recompiler/frontend/maxwell/translate/impl/logic_operation.cpp
index 89e5cd6de..92cd27ed4 100644
--- a/src/shader_recompiler/frontend/maxwell/translate/impl/logic_operation.cpp
+++ b/src/shader_recompiler/frontend/maxwell/translate/impl/logic_operation.cpp
@@ -44,9 +44,6 @@ void LOP(TranslatorVisitor& v, u64 insn, IR::U32 op_b, bool x, bool cc, bool inv
     if (x) {
         throw NotImplementedException("X");
     }
-    if (cc) {
-        throw NotImplementedException("CC");
-    }
     IR::U32 op_a{v.X(lop.src_reg)};
     if (inv_a != 0) {
         op_a = v.ir.BitwiseNot(op_a);
@@ -60,6 +57,17 @@ void LOP(TranslatorVisitor& v, u64 insn, IR::U32 op_b, bool x, bool cc, bool inv
         const IR::U1 pred_result{PredicateOperation(v.ir, result, *pred_op)};
         v.ir.SetPred(dest_pred, pred_result);
     }
+    if (cc) {
+        if (bit_op == LogicalOp::PASS_B) {
+            v.SetZFlag(v.ir.IEqual(result, v.ir.Imm32(0)));
+            v.SetSFlag(v.ir.ILessThan(result, v.ir.Imm32(0), true));
+        } else {
+            v.SetZFlag(v.ir.GetZeroFromOp(result));
+            v.SetSFlag(v.ir.GetSignFromOp(result));
+        }
+        v.ResetCFlag();
+        v.ResetOFlag();
+    }
     v.X(lop.dest_reg, result);
 }
 
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