From f91859efd259995806c2944f7941b105b58300d3 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Sat, 20 Mar 2021 05:04:12 -0300
Subject: shader: Implement I2F

---
 .../backend/spirv/emit_context.cpp                 |  2 +
 src/shader_recompiler/backend/spirv/emit_spirv.h   | 13 ++++++
 .../backend/spirv/emit_spirv_convert.cpp           | 48 ++++++++++++++++++++++
 .../backend/spirv/emit_spirv_integer.cpp           |  4 ++
 4 files changed, 67 insertions(+)

(limited to 'src/shader_recompiler/backend')

diff --git a/src/shader_recompiler/backend/spirv/emit_context.cpp b/src/shader_recompiler/backend/spirv/emit_context.cpp
index 6c79b611b..6c8f16562 100644
--- a/src/shader_recompiler/backend/spirv/emit_context.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_context.cpp
@@ -89,6 +89,8 @@ Id EmitContext::Def(const IR::Value& value) {
         return value.U1() ? true_value : false_value;
     case IR::Type::U32:
         return Constant(U32[1], value.U32());
+    case IR::Type::U64:
+        return Constant(U64, value.U64());
     case IR::Type::F32:
         return Constant(F32[1], value.F32());
     case IR::Type::F64:
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index ae121f534..1fe65f8a9 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -243,6 +243,7 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b);
 Id EmitINeg32(EmitContext& ctx, Id value);
 Id EmitINeg64(EmitContext& ctx, Id value);
 Id EmitIAbs32(EmitContext& ctx, Id value);
+Id EmitIAbs64(EmitContext& ctx, Id value);
 Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
 Id EmitShiftLeftLogical64(EmitContext& ctx, Id base, Id shift);
 Id EmitShiftRightLogical32(EmitContext& ctx, Id base, Id shift);
@@ -302,16 +303,28 @@ Id EmitConvertF16F32(EmitContext& ctx, Id value);
 Id EmitConvertF32F16(EmitContext& ctx, Id value);
 Id EmitConvertF32F64(EmitContext& ctx, Id value);
 Id EmitConvertF64F32(EmitContext& ctx, Id value);
+Id EmitConvertF16S8(EmitContext& ctx, Id value);
+Id EmitConvertF16S16(EmitContext& ctx, Id value);
 Id EmitConvertF16S32(EmitContext& ctx, Id value);
 Id EmitConvertF16S64(EmitContext& ctx, Id value);
+Id EmitConvertF16U8(EmitContext& ctx, Id value);
+Id EmitConvertF16U16(EmitContext& ctx, Id value);
 Id EmitConvertF16U32(EmitContext& ctx, Id value);
 Id EmitConvertF16U64(EmitContext& ctx, Id value);
+Id EmitConvertF32S8(EmitContext& ctx, Id value);
+Id EmitConvertF32S16(EmitContext& ctx, Id value);
 Id EmitConvertF32S32(EmitContext& ctx, Id value);
 Id EmitConvertF32S64(EmitContext& ctx, Id value);
+Id EmitConvertF32U8(EmitContext& ctx, Id value);
+Id EmitConvertF32U16(EmitContext& ctx, Id value);
 Id EmitConvertF32U32(EmitContext& ctx, Id value);
 Id EmitConvertF32U64(EmitContext& ctx, Id value);
+Id EmitConvertF64S8(EmitContext& ctx, Id value);
+Id EmitConvertF64S16(EmitContext& ctx, Id value);
 Id EmitConvertF64S32(EmitContext& ctx, Id value);
 Id EmitConvertF64S64(EmitContext& ctx, Id value);
+Id EmitConvertF64U8(EmitContext& ctx, Id value);
+Id EmitConvertF64U16(EmitContext& ctx, Id value);
 Id EmitConvertF64U32(EmitContext& ctx, Id value);
 Id EmitConvertF64U64(EmitContext& ctx, Id value);
 Id EmitBindlessImageSampleImplicitLod(EmitContext&);
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp
index 2aff673aa..757165626 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_convert.cpp
@@ -102,6 +102,14 @@ Id EmitConvertF64F32(EmitContext& ctx, Id value) {
     return ctx.OpFConvert(ctx.F64[1], value);
 }
 
+Id EmitConvertF16S8(EmitContext& ctx, Id value) {
+    return ctx.OpConvertSToF(ctx.F16[1], value);
+}
+
+Id EmitConvertF16S16(EmitContext& ctx, Id value) {
+    return ctx.OpConvertSToF(ctx.F16[1], value);
+}
+
 Id EmitConvertF16S32(EmitContext& ctx, Id value) {
     return ctx.OpConvertSToF(ctx.F16[1], value);
 }
@@ -110,6 +118,14 @@ Id EmitConvertF16S64(EmitContext& ctx, Id value) {
     return ctx.OpConvertSToF(ctx.F16[1], value);
 }
 
+Id EmitConvertF16U8(EmitContext& ctx, Id value) {
+    return ctx.OpConvertUToF(ctx.F16[1], value);
+}
+
+Id EmitConvertF16U16(EmitContext& ctx, Id value) {
+    return ctx.OpConvertUToF(ctx.F16[1], value);
+}
+
 Id EmitConvertF16U32(EmitContext& ctx, Id value) {
     return ctx.OpConvertUToF(ctx.F16[1], value);
 }
@@ -118,6 +134,14 @@ Id EmitConvertF16U64(EmitContext& ctx, Id value) {
     return ctx.OpConvertUToF(ctx.F16[1], value);
 }
 
+Id EmitConvertF32S8(EmitContext& ctx, Id value) {
+    return ctx.OpConvertSToF(ctx.F32[1], ctx.OpUConvert(ctx.U8, value));
+}
+
+Id EmitConvertF32S16(EmitContext& ctx, Id value) {
+    return ctx.OpConvertSToF(ctx.F32[1], ctx.OpUConvert(ctx.U16, value));
+}
+
 Id EmitConvertF32S32(EmitContext& ctx, Id value) {
     return ctx.OpConvertSToF(ctx.F32[1], value);
 }
@@ -126,6 +150,14 @@ Id EmitConvertF32S64(EmitContext& ctx, Id value) {
     return ctx.OpConvertSToF(ctx.F32[1], value);
 }
 
+Id EmitConvertF32U8(EmitContext& ctx, Id value) {
+    return ctx.OpConvertUToF(ctx.F32[1], ctx.OpUConvert(ctx.U8, value));
+}
+
+Id EmitConvertF32U16(EmitContext& ctx, Id value) {
+    return ctx.OpConvertUToF(ctx.F32[1], ctx.OpUConvert(ctx.U16, value));
+}
+
 Id EmitConvertF32U32(EmitContext& ctx, Id value) {
     return ctx.OpConvertUToF(ctx.F32[1], value);
 }
@@ -134,6 +166,14 @@ Id EmitConvertF32U64(EmitContext& ctx, Id value) {
     return ctx.OpConvertUToF(ctx.F32[1], value);
 }
 
+Id EmitConvertF64S8(EmitContext& ctx, Id value) {
+    return ctx.OpConvertSToF(ctx.F64[1], ctx.OpUConvert(ctx.U8, value));
+}
+
+Id EmitConvertF64S16(EmitContext& ctx, Id value) {
+    return ctx.OpConvertSToF(ctx.F64[1], ctx.OpUConvert(ctx.U16, value));
+}
+
 Id EmitConvertF64S32(EmitContext& ctx, Id value) {
     return ctx.OpConvertSToF(ctx.F64[1], value);
 }
@@ -142,6 +182,14 @@ Id EmitConvertF64S64(EmitContext& ctx, Id value) {
     return ctx.OpConvertSToF(ctx.F64[1], value);
 }
 
+Id EmitConvertF64U8(EmitContext& ctx, Id value) {
+    return ctx.OpConvertUToF(ctx.F64[1], ctx.OpUConvert(ctx.U8, value));
+}
+
+Id EmitConvertF64U16(EmitContext& ctx, Id value) {
+    return ctx.OpConvertUToF(ctx.F64[1], ctx.OpUConvert(ctx.U16, value));
+}
+
 Id EmitConvertF64U32(EmitContext& ctx, Id value) {
     return ctx.OpConvertUToF(ctx.F64[1], value);
 }
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index c9de204b0..a9c5e9cca 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -70,6 +70,10 @@ Id EmitIAbs32(EmitContext& ctx, Id value) {
     return ctx.OpSAbs(ctx.U32[1], value);
 }
 
+Id EmitIAbs64(EmitContext& ctx, Id value) {
+    return ctx.OpSAbs(ctx.U64, value);
+}
+
 Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
     return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
 }
-- 
cgit v1.2.3