From cc55d289494c991e7e0e456e428a110569708c2e Mon Sep 17 00:00:00 2001
From: ameerj <52414509+ameerj@users.noreply.github.com>
Date: Thu, 25 Feb 2021 00:46:40 -0500
Subject: shader: Implement SHR

---
 src/shader_recompiler/backend/spirv/emit_spirv.h           |  5 +++--
 src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp | 12 ++++++++----
 2 files changed, 11 insertions(+), 6 deletions(-)

(limited to 'src/shader_recompiler/backend')

diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index 4b74cf04d..90afbcc90 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -219,14 +219,15 @@ Id EmitIMul32(EmitContext& ctx, Id a, Id b);
 Id EmitINeg32(EmitContext& ctx, Id value);
 Id EmitIAbs32(EmitContext& ctx, Id value);
 Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift);
-void EmitShiftRightLogical32(EmitContext& ctx);
-void EmitShiftRightArithmetic32(EmitContext& ctx);
+Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b);
+Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b);
 Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b);
 Id EmitBitwiseOr32(EmitContext& ctx, Id a, Id b);
 Id EmitBitwiseXor32(EmitContext& ctx, Id a, Id b);
 Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count);
 Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count);
 Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
+Id EmitBitReverse32(EmitContext& ctx, Id value);
 Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
 Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs);
 Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 8aaa0e381..406df1b78 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -70,12 +70,12 @@ Id EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
     return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
 }
 
-void EmitShiftRightLogical32(EmitContext&) {
-    throw NotImplementedException("SPIR-V Instruction");
+Id EmitShiftRightLogical32(EmitContext& ctx, Id a, Id b) {
+    return ctx.OpShiftRightLogical(ctx.U32[1], a, b);
 }
 
-void EmitShiftRightArithmetic32(EmitContext&) {
-    throw NotImplementedException("SPIR-V Instruction");
+Id EmitShiftRightArithmetic32(EmitContext& ctx, Id a, Id b) {
+    return ctx.OpShiftRightArithmetic(ctx.U32[1], a, b);
 }
 
 Id EmitBitwiseAnd32(EmitContext& ctx, Id a, Id b) {
@@ -102,6 +102,10 @@ Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
     return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count);
 }
 
+Id EmitBitReverse32(EmitContext& ctx, Id value) {
+    return ctx.OpBitReverse(ctx.U32[1], value);
+}
+
 Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
     return ctx.OpSLessThan(ctx.U1, lhs, rhs);
 }
-- 
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