From cbfb7d182a4e90e4e263696d1fca35e47d3eabb4 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Sun, 14 Feb 2021 20:15:42 -0300
Subject: shader: Support SSA loops on IR

---
 src/shader_recompiler/backend/spirv/emit_spirv.h             | 12 ++++++------
 src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp   |  8 ++++----
 src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp | 10 +++++-----
 3 files changed, 15 insertions(+), 15 deletions(-)

(limited to 'src/shader_recompiler/backend/spirv')

diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index 46ec7a1bb..6b09757d1 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -159,10 +159,10 @@ private:
     Id EmitWorkgroupId(EmitContext& ctx);
     Id EmitLocalInvocationId(EmitContext& ctx);
     Id EmitUndefU1(EmitContext& ctx);
-    void EmitUndefU8(EmitContext& ctx);
-    void EmitUndefU16(EmitContext& ctx);
-    void EmitUndefU32(EmitContext& ctx);
-    void EmitUndefU64(EmitContext& ctx);
+    Id EmitUndefU8(EmitContext& ctx);
+    Id EmitUndefU16(EmitContext& ctx);
+    Id EmitUndefU32(EmitContext& ctx);
+    Id EmitUndefU64(EmitContext& ctx);
     void EmitLoadGlobalU8(EmitContext& ctx);
     void EmitLoadGlobalS8(EmitContext& ctx);
     void EmitLoadGlobalU16(EmitContext& ctx);
@@ -297,12 +297,12 @@ private:
     void EmitBitFieldInsert(EmitContext& ctx);
     void EmitBitFieldSExtract(EmitContext& ctx);
     Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
-    void EmitSLessThan(EmitContext& ctx);
+    Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
     void EmitULessThan(EmitContext& ctx);
     void EmitIEqual(EmitContext& ctx);
     void EmitSLessThanEqual(EmitContext& ctx);
     void EmitULessThanEqual(EmitContext& ctx);
-    void EmitSGreaterThan(EmitContext& ctx);
+    Id EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs);
     void EmitUGreaterThan(EmitContext& ctx);
     void EmitINotEqual(EmitContext& ctx);
     void EmitSGreaterThanEqual(EmitContext& ctx);
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index 3ef4f3d78..e811a63ab 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -73,8 +73,8 @@ Id EmitSPIRV::EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id coun
     return ctx.OpBitFieldUExtract(ctx.u32[1], base, offset, count);
 }
 
-void EmitSPIRV::EmitSLessThan(EmitContext&) {
-    throw NotImplementedException("SPIR-V Instruction");
+Id EmitSPIRV::EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
+    return ctx.OpSLessThan(ctx.u1, lhs, rhs);
 }
 
 void EmitSPIRV::EmitULessThan(EmitContext&) {
@@ -93,8 +93,8 @@ void EmitSPIRV::EmitULessThanEqual(EmitContext&) {
     throw NotImplementedException("SPIR-V Instruction");
 }
 
-void EmitSPIRV::EmitSGreaterThan(EmitContext&) {
-    throw NotImplementedException("SPIR-V Instruction");
+Id EmitSPIRV::EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
+    return ctx.OpSGreaterThan(ctx.u1, lhs, rhs);
 }
 
 void EmitSPIRV::EmitUGreaterThan(EmitContext&) {
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp
index 859b60a95..a6f542360 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_undefined.cpp
@@ -10,19 +10,19 @@ Id EmitSPIRV::EmitUndefU1(EmitContext& ctx) {
     return ctx.OpUndef(ctx.u1);
 }
 
-void EmitSPIRV::EmitUndefU8(EmitContext&) {
+Id EmitSPIRV::EmitUndefU8(EmitContext&) {
     throw NotImplementedException("SPIR-V Instruction");
 }
 
-void EmitSPIRV::EmitUndefU16(EmitContext&) {
+Id EmitSPIRV::EmitUndefU16(EmitContext&) {
     throw NotImplementedException("SPIR-V Instruction");
 }
 
-void EmitSPIRV::EmitUndefU32(EmitContext&) {
-    throw NotImplementedException("SPIR-V Instruction");
+Id EmitSPIRV::EmitUndefU32(EmitContext& ctx) {
+    return ctx.OpUndef(ctx.u32[1]);
 }
 
-void EmitSPIRV::EmitUndefU64(EmitContext&) {
+Id EmitSPIRV::EmitUndefU64(EmitContext&) {
     throw NotImplementedException("SPIR-V Instruction");
 }
 
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