From 20390c0548d6eef2af67a363ee120a630267b741 Mon Sep 17 00:00:00 2001
From: ameerj <52414509+ameerj@users.noreply.github.com>
Date: Sun, 28 Feb 2021 23:33:53 -0500
Subject: shader: Implement IMNMX

---
 src/shader_recompiler/backend/spirv/emit_spirv.h         |  4 ++++
 .../backend/spirv/emit_spirv_integer.cpp                 | 16 ++++++++++++++++
 2 files changed, 20 insertions(+)

(limited to 'src/shader_recompiler/backend/spirv')

diff --git a/src/shader_recompiler/backend/spirv/emit_spirv.h b/src/shader_recompiler/backend/spirv/emit_spirv.h
index 64c8e9ef6..4d00b235d 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv.h
+++ b/src/shader_recompiler/backend/spirv/emit_spirv.h
@@ -230,6 +230,10 @@ Id EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count);
 Id EmitBitReverse32(EmitContext& ctx, Id value);
 Id EmitBitCount32(EmitContext& ctx, Id value);
 Id EmitBitwiseNot32(EmitContext& ctx, Id a);
+Id EmitSMin32(EmitContext& ctx, Id a, Id b);
+Id EmitUMin32(EmitContext& ctx, Id a, Id b);
+Id EmitSMax32(EmitContext& ctx, Id a, Id b);
+Id EmitUMax32(EmitContext& ctx, Id a, Id b);
 Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs);
 Id EmitULessThan(EmitContext& ctx, Id lhs, Id rhs);
 Id EmitIEqual(EmitContext& ctx, Id lhs, Id rhs);
diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index e49ca7bde..5bdd943a4 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -114,6 +114,22 @@ Id EmitBitwiseNot32(EmitContext& ctx, Id a) {
     return ctx.OpNot(ctx.U32[1], a);
 }
 
+Id EmitSMin32(EmitContext& ctx, Id a, Id b) {
+    return ctx.OpSMin(ctx.U32[1], a, b);
+}
+
+Id EmitUMin32(EmitContext& ctx, Id a, Id b) {
+    return ctx.OpUMin(ctx.U32[1], a, b);
+}
+
+Id EmitSMax32(EmitContext& ctx, Id a, Id b) {
+    return ctx.OpSMax(ctx.U32[1], a, b);
+}
+
+Id EmitUMax32(EmitContext& ctx, Id a, Id b) {
+    return ctx.OpUMax(ctx.U32[1], a, b);
+}
+
 Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
     return ctx.OpSLessThan(ctx.U1, lhs, rhs);
 }
-- 
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