From b5d7279d878211654b4abb165d94af763a365f47 Mon Sep 17 00:00:00 2001
From: ReinUsesLisp <reinuseslisp@airmail.cc>
Date: Tue, 16 Feb 2021 04:10:22 -0300
Subject: spirv: Initial bindings support

---
 .../backend/spirv/emit_spirv_integer.cpp                 | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp')

diff --git a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
index e811a63ab..32af94a73 100644
--- a/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
+++ b/src/shader_recompiler/backend/spirv/emit_spirv_integer.cpp
@@ -10,7 +10,7 @@ Id EmitSPIRV::EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
     if (inst->HasAssociatedPseudoOperation()) {
         throw NotImplementedException("Pseudo-operations on IAdd32");
     }
-    return ctx.OpIAdd(ctx.u32[1], a, b);
+    return ctx.OpIAdd(ctx.U32[1], a, b);
 }
 
 void EmitSPIRV::EmitIAdd64(EmitContext&) {
@@ -18,7 +18,7 @@ void EmitSPIRV::EmitIAdd64(EmitContext&) {
 }
 
 Id EmitSPIRV::EmitISub32(EmitContext& ctx, Id a, Id b) {
-    return ctx.OpISub(ctx.u32[1], a, b);
+    return ctx.OpISub(ctx.U32[1], a, b);
 }
 
 void EmitSPIRV::EmitISub64(EmitContext&) {
@@ -26,7 +26,7 @@ void EmitSPIRV::EmitISub64(EmitContext&) {
 }
 
 Id EmitSPIRV::EmitIMul32(EmitContext& ctx, Id a, Id b) {
-    return ctx.OpIMul(ctx.u32[1], a, b);
+    return ctx.OpIMul(ctx.U32[1], a, b);
 }
 
 void EmitSPIRV::EmitINeg32(EmitContext&) {
@@ -38,7 +38,7 @@ void EmitSPIRV::EmitIAbs32(EmitContext&) {
 }
 
 Id EmitSPIRV::EmitShiftLeftLogical32(EmitContext& ctx, Id base, Id shift) {
-    return ctx.OpShiftLeftLogical(ctx.u32[1], base, shift);
+    return ctx.OpShiftLeftLogical(ctx.U32[1], base, shift);
 }
 
 void EmitSPIRV::EmitShiftRightLogical32(EmitContext&) {
@@ -70,11 +70,11 @@ void EmitSPIRV::EmitBitFieldSExtract(EmitContext&) {
 }
 
 Id EmitSPIRV::EmitBitFieldUExtract(EmitContext& ctx, Id base, Id offset, Id count) {
-    return ctx.OpBitFieldUExtract(ctx.u32[1], base, offset, count);
+    return ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count);
 }
 
 Id EmitSPIRV::EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
-    return ctx.OpSLessThan(ctx.u1, lhs, rhs);
+    return ctx.OpSLessThan(ctx.U1, lhs, rhs);
 }
 
 void EmitSPIRV::EmitULessThan(EmitContext&) {
@@ -94,7 +94,7 @@ void EmitSPIRV::EmitULessThanEqual(EmitContext&) {
 }
 
 Id EmitSPIRV::EmitSGreaterThan(EmitContext& ctx, Id lhs, Id rhs) {
-    return ctx.OpSGreaterThan(ctx.u1, lhs, rhs);
+    return ctx.OpSGreaterThan(ctx.U1, lhs, rhs);
 }
 
 void EmitSPIRV::EmitUGreaterThan(EmitContext&) {
@@ -110,7 +110,7 @@ void EmitSPIRV::EmitSGreaterThanEqual(EmitContext&) {
 }
 
 Id EmitSPIRV::EmitUGreaterThanEqual(EmitContext& ctx, Id lhs, Id rhs) {
-    return ctx.OpUGreaterThanEqual(ctx.u1, lhs, rhs);
+    return ctx.OpUGreaterThanEqual(ctx.U1, lhs, rhs);
 }
 
 void EmitSPIRV::EmitLogicalOr(EmitContext&) {
-- 
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