From 0f40b0e61ccc04216e0840e092dfe3051716b8b6 Mon Sep 17 00:00:00 2001
From: ameerj <52414509+ameerj@users.noreply.github.com>
Date: Fri, 21 May 2021 20:56:46 -0400
Subject: glsl: Implement a few Integer instructions

---
 src/shader_recompiler/backend/glsl/reg_alloc.cpp | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

(limited to 'src/shader_recompiler/backend/glsl/reg_alloc.cpp')

diff --git a/src/shader_recompiler/backend/glsl/reg_alloc.cpp b/src/shader_recompiler/backend/glsl/reg_alloc.cpp
index f4886dbfd..3cfa16fea 100644
--- a/src/shader_recompiler/backend/glsl/reg_alloc.cpp
+++ b/src/shader_recompiler/backend/glsl/reg_alloc.cpp
@@ -57,9 +57,10 @@ std::string RegAlloc::Consume(const IR::Value& value) {
 std::string RegAlloc::Consume(IR::Inst& inst) {
     const Id id{inst.Definition<Id>()};
     inst.DestructiveRemoveUsage();
-    if (!inst.HasUses()) {
-        Free(id);
-    }
+    // TODO: reuse variables of same type if possible
+    // if (!inst.HasUses()) {
+    //     Free(id);
+    // }
     return Representation(inst.Definition<Id>());
 }
 
@@ -69,14 +70,24 @@ std::string RegAlloc::GetType(Type type, u32 index) {
     }
     register_defined[index] = true;
     switch (type) {
+    case Type::U1:
+        return "bool ";
     case Type::U32:
         return "uint ";
     case Type::S32:
         return "int ";
     case Type::F32:
         return "float ";
-    default:
+    case Type::U64:
+        return "uint64_t ";
+    case Type::U32x2:
+        return "uvec2 ";
+    case Type::F32x2:
+        return "vec2 ";
+    case Type::Void:
         return "";
+    default:
+        throw NotImplementedException("Type {}", type);
     }
 }
 
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