From 4dc8eb40be94e8376e0f2d2f59a5e1a85590d6b1 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Thu, 18 Dec 2014 11:11:30 -0500 Subject: armemu: Set GE flags correctly for SSUB16, SADD16, SSAX, and SASX. --- src/core/arm/interpreter/armemu.cpp | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) (limited to 'src/core/arm') diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp index b9ac8b9ad..f4452f356 100644 --- a/src/core/arm/interpreter/armemu.cpp +++ b/src/core/arm/interpreter/armemu.cpp @@ -5839,21 +5839,46 @@ L_stm_s_takeabort: const s16 rm_lo = (state->Reg[rm_idx] & 0xFFFF); const s16 rm_hi = ((state->Reg[rm_idx] >> 16) & 0xFFFF); + s32 lo_result; + s32 hi_result; + // SSUB16 if ((instr & 0xFF0) == 0xf70) { - state->Reg[rd_idx] = ((rn_lo - rm_lo) & 0xFFFF) | (((rn_hi - rm_hi) & 0xFFFF) << 16); + lo_result = (rn_lo - rm_lo); + hi_result = (rn_hi - rm_hi); } // SADD16 else if ((instr & 0xFF0) == 0xf10) { - state->Reg[rd_idx] = ((rn_lo + rm_lo) & 0xFFFF) | (((rn_hi + rm_hi) & 0xFFFF) << 16); + lo_result = (rn_lo + rm_lo); + hi_result = (rn_hi + rm_hi); } // SSAX else if ((instr & 0xFF0) == 0xf50) { - state->Reg[rd_idx] = ((rn_lo + rm_hi) & 0xFFFF) | (((rn_hi - rm_lo) & 0xFFFF) << 16); + lo_result = (rn_lo + rm_hi); + hi_result = (rn_hi - rm_lo); } // SASX else { - state->Reg[rd_idx] = ((rn_lo - rm_hi) & 0xFFFF) | (((rn_hi + rm_lo) & 0xFFFF) << 16); + lo_result = (rn_lo - rm_hi); + hi_result = (rn_hi + rm_lo); + } + + state->Reg[rd_idx] = (lo_result & 0xFFFF) | ((hi_result & 0xFFFF) << 16); + + if (lo_result >= 0) { + state->Cpsr |= (1 << 16); + state->Cpsr |= (1 << 17); + } else { + state->Cpsr &= ~(1 << 16); + state->Cpsr &= ~(1 << 17); + } + + if (hi_result >= 0) { + state->Cpsr |= (1 << 18); + state->Cpsr |= (1 << 19); + } else { + state->Cpsr &= ~(1 << 18); + state->Cpsr &= ~(1 << 19); } return 1; } else { -- cgit v1.2.3