From ce4d271a53e79814f66a46bd69a8970ea3849ee9 Mon Sep 17 00:00:00 2001 From: bunnei Date: Sun, 11 May 2014 22:14:13 -0400 Subject: added option to set CPSR register to arm_interface --- src/core/arm/interpreter/arm_interpreter.cpp | 8 ++++++++ src/core/arm/interpreter/arm_interpreter.h | 6 ++++++ 2 files changed, 14 insertions(+) (limited to 'src/core/arm/interpreter') diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp index 4045779d7..81147f2d4 100644 --- a/src/core/arm/interpreter/arm_interpreter.cpp +++ b/src/core/arm/interpreter/arm_interpreter.cpp @@ -77,6 +77,14 @@ u32 ARM_Interpreter::GetCPSR() const { return m_state->Cpsr; } +/** + * Set the current CPSR register + * @param cpsr Value to set CPSR to + */ +void ARM_Interpreter::SetCPSR(u32 cpsr) { + m_state->Cpsr = cpsr; +} + /** * Returns the number of clock ticks since the last reset * @return Returns number of clock ticks diff --git a/src/core/arm/interpreter/arm_interpreter.h b/src/core/arm/interpreter/arm_interpreter.h index 625c0c652..78b188bee 100644 --- a/src/core/arm/interpreter/arm_interpreter.h +++ b/src/core/arm/interpreter/arm_interpreter.h @@ -48,6 +48,12 @@ public: */ u32 GetCPSR() const; + /** + * Set the current CPSR register + * @param cpsr Value to set CPSR to + */ + void SetCPSR(u32 cpsr); + /** * Returns the number of clock ticks since the last reset * @return Returns number of clock ticks -- cgit v1.2.3 From fbc04ad0c7c2bafde1b7b50957799c7bbab8f77b Mon Sep 17 00:00:00 2001 From: bunnei Date: Sat, 17 May 2014 13:48:27 -0400 Subject: ignore thumbemu 0xDEADCODE debugging catch on MCR --- src/core/arm/interpreter/armemu.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/core/arm/interpreter') diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp index 32e315f4b..aa1ff17bb 100644 --- a/src/core/arm/interpreter/armemu.cpp +++ b/src/core/arm/interpreter/armemu.cpp @@ -4478,8 +4478,7 @@ ARMul_Emulate26 (ARMul_State * state) isize) & R15PCBITS)); #endif - } - else + } else if (instr != 0xDEADC0DE) // thumbemu uses 0xDEADCODE for debugging to catch non updates ARMul_MCR (state, instr, DEST); } -- cgit v1.2.3 From 29930ac1101ca12213169d9a21c45efa0d07a374 Mon Sep 17 00:00:00 2001 From: bunnei Date: Mon, 19 May 2014 22:19:10 -0400 Subject: VFP: disable DBG messages because they spam the console with unimportant skyeye junk --- src/core/arm/interpreter/vfp/vfp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/core/arm/interpreter') diff --git a/src/core/arm/interpreter/vfp/vfp.h b/src/core/arm/interpreter/vfp/vfp.h index f738a615b..bbf4caeb0 100644 --- a/src/core/arm/interpreter/vfp/vfp.h +++ b/src/core/arm/interpreter/vfp/vfp.h @@ -21,7 +21,7 @@ #ifndef __VFP_H__ #define __VFP_H__ -#define DBG(...) DEBUG_LOG(ARM11, __VA_ARGS__) +#define DBG(...) //DEBUG_LOG(ARM11, __VA_ARGS__) #define vfpdebug //printf -- cgit v1.2.3 From 49dc2ce8ac4fc37a008fa28e0771c8c74c576b05 Mon Sep 17 00:00:00 2001 From: bunnei Date: Tue, 20 May 2014 18:50:16 -0400 Subject: ARM_Interface: added SaveContext and LoadContext functions for HLE thread switching --- src/core/arm/interpreter/arm_interpreter.cpp | 36 ++++++++++++++++++++++++++++ src/core/arm/interpreter/arm_interpreter.h | 12 ++++++++++ 2 files changed, 48 insertions(+) (limited to 'src/core/arm/interpreter') diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp index c21ff0464..b8c46cdfc 100644 --- a/src/core/arm/interpreter/arm_interpreter.cpp +++ b/src/core/arm/interpreter/arm_interpreter.cpp @@ -101,3 +101,39 @@ void ARM_Interpreter::ExecuteInstructions(int num_instructions) { m_state->NumInstrsToExecute = num_instructions; ARMul_Emulate32(m_state); } + +/** + * Saves the current CPU context + * @param ctx Thread context to save + * @todo Do we need to save Reg[15] and NextInstr? + */ +void ARM_Interpreter::SaveContext(ThreadContext& ctx) { + memcpy(ctx.cpu_registers, m_state->Reg, sizeof(ctx.cpu_registers)); + memcpy(ctx.fpu_registers, m_state->ExtReg, sizeof(ctx.fpu_registers)); + + ctx.sp = m_state->Reg[13]; + ctx.lr = m_state->Reg[14]; + ctx.pc = m_state->pc; + ctx.cpsr = m_state->Cpsr; + + ctx.fpscr = m_state->VFP[1]; + ctx.fpexc = m_state->VFP[2]; +} + +/** + * Loads a CPU context + * @param ctx Thread context to load + * @param Do we need to load Reg[15] and NextInstr? + */ +void ARM_Interpreter::LoadContext(const ThreadContext& ctx) { + memcpy(m_state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers)); + memcpy(m_state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers)); + + m_state->Reg[13] = ctx.sp; + m_state->Reg[14] = ctx.lr; + m_state->pc = ctx.pc; + m_state->Cpsr = ctx.cpsr; + + m_state->VFP[1] = ctx.fpscr; + m_state->VFP[2] = ctx.fpexc; +} diff --git a/src/core/arm/interpreter/arm_interpreter.h b/src/core/arm/interpreter/arm_interpreter.h index 474ba3e45..15240568c 100644 --- a/src/core/arm/interpreter/arm_interpreter.h +++ b/src/core/arm/interpreter/arm_interpreter.h @@ -60,6 +60,18 @@ public: */ u64 GetTicks() const; + /** + * Saves the current CPU context + * @param ctx Thread context to save + */ + void SaveContext(ThreadContext& ctx); + + /** + * Loads a CPU context + * @param ctx Thread context to load + */ + void LoadContext(const ThreadContext& ctx); + protected: /** -- cgit v1.2.3 From 001280245685ade50326301409e8aee28602504d Mon Sep 17 00:00:00 2001 From: bunnei Date: Tue, 20 May 2014 18:52:54 -0400 Subject: ARM_Interpreter/ARM_Interface: Fixed member variable naming to be consistent with style guide --- src/core/arm/interpreter/arm_interpreter.cpp | 78 ++++++++++++++-------------- src/core/arm/interpreter/arm_interpreter.h | 2 +- 2 files changed, 40 insertions(+), 40 deletions(-) (limited to 'src/core/arm/interpreter') diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp index b8c46cdfc..a9ec94820 100644 --- a/src/core/arm/interpreter/arm_interpreter.cpp +++ b/src/core/arm/interpreter/arm_interpreter.cpp @@ -9,30 +9,30 @@ const static cpu_config_t s_arm11_cpu_info = { }; ARM_Interpreter::ARM_Interpreter() { - m_state = new ARMul_State; + state = new ARMul_State; ARMul_EmulateInit(); - ARMul_NewState(m_state); + ARMul_NewState(state); - m_state->abort_model = 0; - m_state->cpu = (cpu_config_t*)&s_arm11_cpu_info; - m_state->bigendSig = LOW; + state->abort_model = 0; + state->cpu = (cpu_config_t*)&s_arm11_cpu_info; + state->bigendSig = LOW; - ARMul_SelectProcessor(m_state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); - m_state->lateabtSig = LOW; - mmu_init(m_state); + ARMul_SelectProcessor(state, ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop); + state->lateabtSig = LOW; + mmu_init(state); // Reset the core to initial state - ARMul_Reset(m_state); - m_state->NextInstr = 0; - m_state->Emulate = 3; + ARMul_Reset(state); + state->NextInstr = 0; + state->Emulate = 3; - m_state->pc = m_state->Reg[15] = 0x00000000; - m_state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack + state->pc = state->Reg[15] = 0x00000000; + state->Reg[13] = 0x10000000; // Set stack pointer to the top of the stack } ARM_Interpreter::~ARM_Interpreter() { - delete m_state; + delete state; } /** @@ -40,7 +40,7 @@ ARM_Interpreter::~ARM_Interpreter() { * @param addr Address to set PC to */ void ARM_Interpreter::SetPC(u32 pc) { - m_state->pc = m_state->Reg[15] = pc; + state->pc = state->Reg[15] = pc; } /* @@ -48,7 +48,7 @@ void ARM_Interpreter::SetPC(u32 pc) { * @return Returns current PC */ u32 ARM_Interpreter::GetPC() const { - return m_state->pc; + return state->pc; } /** @@ -57,7 +57,7 @@ u32 ARM_Interpreter::GetPC() const { * @return Returns the value in the register */ u32 ARM_Interpreter::GetReg(int index) const { - return m_state->Reg[index]; + return state->Reg[index]; } /** @@ -66,7 +66,7 @@ u32 ARM_Interpreter::GetReg(int index) const { * @param value Value to set register to */ void ARM_Interpreter::SetReg(int index, u32 value) { - m_state->Reg[index] = value; + state->Reg[index] = value; } /** @@ -74,7 +74,7 @@ void ARM_Interpreter::SetReg(int index, u32 value) { * @return Returns the value of the CPSR register */ u32 ARM_Interpreter::GetCPSR() const { - return m_state->Cpsr; + return state->Cpsr; } /** @@ -82,7 +82,7 @@ u32 ARM_Interpreter::GetCPSR() const { * @param cpsr Value to set CPSR to */ void ARM_Interpreter::SetCPSR(u32 cpsr) { - m_state->Cpsr = cpsr; + state->Cpsr = cpsr; } /** @@ -90,7 +90,7 @@ void ARM_Interpreter::SetCPSR(u32 cpsr) { * @return Returns number of clock ticks */ u64 ARM_Interpreter::GetTicks() const { - return ARMul_Time(m_state); + return ARMul_Time(state); } /** @@ -98,8 +98,8 @@ u64 ARM_Interpreter::GetTicks() const { * @param num_instructions Number of instructions to executes */ void ARM_Interpreter::ExecuteInstructions(int num_instructions) { - m_state->NumInstrsToExecute = num_instructions; - ARMul_Emulate32(m_state); + state->NumInstrsToExecute = num_instructions; + ARMul_Emulate32(state); } /** @@ -108,16 +108,16 @@ void ARM_Interpreter::ExecuteInstructions(int num_instructions) { * @todo Do we need to save Reg[15] and NextInstr? */ void ARM_Interpreter::SaveContext(ThreadContext& ctx) { - memcpy(ctx.cpu_registers, m_state->Reg, sizeof(ctx.cpu_registers)); - memcpy(ctx.fpu_registers, m_state->ExtReg, sizeof(ctx.fpu_registers)); + memcpy(ctx.cpu_registers, state->Reg, sizeof(ctx.cpu_registers)); + memcpy(ctx.fpu_registers, state->ExtReg, sizeof(ctx.fpu_registers)); - ctx.sp = m_state->Reg[13]; - ctx.lr = m_state->Reg[14]; - ctx.pc = m_state->pc; - ctx.cpsr = m_state->Cpsr; + ctx.sp = state->Reg[13]; + ctx.lr = state->Reg[14]; + ctx.pc = state->pc; + ctx.cpsr = state->Cpsr; - ctx.fpscr = m_state->VFP[1]; - ctx.fpexc = m_state->VFP[2]; + ctx.fpscr = state->VFP[1]; + ctx.fpexc = state->VFP[2]; } /** @@ -126,14 +126,14 @@ void ARM_Interpreter::SaveContext(ThreadContext& ctx) { * @param Do we need to load Reg[15] and NextInstr? */ void ARM_Interpreter::LoadContext(const ThreadContext& ctx) { - memcpy(m_state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers)); - memcpy(m_state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers)); + memcpy(state->Reg, ctx.cpu_registers, sizeof(ctx.cpu_registers)); + memcpy(state->ExtReg, ctx.fpu_registers, sizeof(ctx.fpu_registers)); - m_state->Reg[13] = ctx.sp; - m_state->Reg[14] = ctx.lr; - m_state->pc = ctx.pc; - m_state->Cpsr = ctx.cpsr; + state->Reg[13] = ctx.sp; + state->Reg[14] = ctx.lr; + state->pc = ctx.pc; + state->Cpsr = ctx.cpsr; - m_state->VFP[1] = ctx.fpscr; - m_state->VFP[2] = ctx.fpexc; + state->VFP[1] = ctx.fpscr; + state->VFP[2] = ctx.fpexc; } diff --git a/src/core/arm/interpreter/arm_interpreter.h b/src/core/arm/interpreter/arm_interpreter.h index 15240568c..6a531e497 100644 --- a/src/core/arm/interpreter/arm_interpreter.h +++ b/src/core/arm/interpreter/arm_interpreter.h @@ -82,6 +82,6 @@ protected: private: - ARMul_State* m_state; + ARMul_State* state; }; -- cgit v1.2.3 From 22eb9a8981c9b4283e37f7d403c598402339ed7f Mon Sep 17 00:00:00 2001 From: bunnei Date: Tue, 20 May 2014 22:25:40 -0400 Subject: armemu: missed rename of "Syscall" to "SVC" --- src/core/arm/interpreter/armemu.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/core/arm/interpreter') diff --git a/src/core/arm/interpreter/armemu.cpp b/src/core/arm/interpreter/armemu.cpp index aa1ff17bb..e5dc7bd44 100644 --- a/src/core/arm/interpreter/armemu.cpp +++ b/src/core/arm/interpreter/armemu.cpp @@ -4548,7 +4548,7 @@ ARMul_Emulate26 (ARMul_State * state) // ARMul_OSHandleSWI (state, BITS (0, 23)); // break; //} - HLE::CallSyscall(instr); + HLE::CallSVC(instr); ARMul_Abort (state, ARMul_SWIV); break; } -- cgit v1.2.3 From a721a4eb33a06b532e36e5a49578abd8338d0d28 Mon Sep 17 00:00:00 2001 From: bunnei Date: Tue, 20 May 2014 22:26:40 -0400 Subject: arm: removed include of windows.h from armdefs.h to arminit.c (only module that uses it) --- src/core/arm/interpreter/armdefs.h | 4 ---- src/core/arm/interpreter/arminit.cpp | 3 +++ 2 files changed, 3 insertions(+), 4 deletions(-) (limited to 'src/core/arm/interpreter') diff --git a/src/core/arm/interpreter/armdefs.h b/src/core/arm/interpreter/armdefs.h index 5b2abc7f7..d8eae4d3f 100644 --- a/src/core/arm/interpreter/armdefs.h +++ b/src/core/arm/interpreter/armdefs.h @@ -24,10 +24,6 @@ #include "common/platform.h" -#if EMU_PLATFORM == PLATFORM_WINDOWS -#include -#endif - //teawater add for arm2x86 2005.02.14------------------------------------------- // koodailar remove it for mingw 2005.12.18---------------- //anthonylee modify it for portable 2007.01.30 diff --git a/src/core/arm/interpreter/arminit.cpp b/src/core/arm/interpreter/arminit.cpp index 2c771cdda..e05667bea 100644 --- a/src/core/arm/interpreter/arminit.cpp +++ b/src/core/arm/interpreter/arminit.cpp @@ -17,8 +17,11 @@ #include "common/platform.h" + #if EMU_PLATFORM == PLATFORM_LINUX #include +#elif EMU_PLATFORM == PLATFORM_WINDOWS +#include #endif #include -- cgit v1.2.3 From 481d936d34c595b994f48b00819bb2c4bcfa7e57 Mon Sep 17 00:00:00 2001 From: bunnei Date: Thu, 22 May 2014 18:47:42 -0400 Subject: arm_interpreter: fixed load context to currently resume a thread --- src/core/arm/interpreter/arm_interpreter.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/core/arm/interpreter') diff --git a/src/core/arm/interpreter/arm_interpreter.cpp b/src/core/arm/interpreter/arm_interpreter.cpp index a9ec94820..17f787b86 100644 --- a/src/core/arm/interpreter/arm_interpreter.cpp +++ b/src/core/arm/interpreter/arm_interpreter.cpp @@ -115,7 +115,7 @@ void ARM_Interpreter::SaveContext(ThreadContext& ctx) { ctx.lr = state->Reg[14]; ctx.pc = state->pc; ctx.cpsr = state->Cpsr; - + ctx.fpscr = state->VFP[1]; ctx.fpexc = state->VFP[2]; } @@ -136,4 +136,7 @@ void ARM_Interpreter::LoadContext(const ThreadContext& ctx) { state->VFP[1] = ctx.fpscr; state->VFP[2] = ctx.fpexc; + + state->Reg[15] = ctx.pc; + state->NextInstr = RESUME; } -- cgit v1.2.3