From fb49ec19c1fb6030fcc960077e82c998290d0ab8 Mon Sep 17 00:00:00 2001
From: Liam <byteslice@airmail.cc>
Date: Fri, 17 Mar 2023 21:26:04 -0400
Subject: kernel: use KTypedAddress for addresses

---
 src/core/arm/dynarmic/arm_dynarmic_32.cpp | 6 +++---
 src/core/arm/dynarmic/arm_dynarmic_32.h   | 6 +++---
 src/core/arm/dynarmic/arm_dynarmic_64.cpp | 8 ++++----
 src/core/arm/dynarmic/arm_dynarmic_64.h   | 6 +++---
 4 files changed, 13 insertions(+), 13 deletions(-)

(limited to 'src/core/arm/dynarmic')

diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.cpp b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
index 2a7570073..aa92d3fc3 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.cpp
@@ -155,7 +155,7 @@ public:
         return std::max<s64>(parent.system.CoreTiming().GetDowncount(), 0);
     }
 
-    bool CheckMemoryAccess(VAddr addr, u64 size, Kernel::DebugWatchpointType type) {
+    bool CheckMemoryAccess(u64 addr, u64 size, Kernel::DebugWatchpointType type) {
         if (!check_memory_access) {
             return true;
         }
@@ -397,7 +397,7 @@ u64 ARM_Dynarmic_32::GetTlsAddress() const {
     return cp15->uro;
 }
 
-void ARM_Dynarmic_32::SetTlsAddress(VAddr address) {
+void ARM_Dynarmic_32::SetTlsAddress(u64 address) {
     cp15->uro = static_cast<u32>(address);
 }
 
@@ -439,7 +439,7 @@ void ARM_Dynarmic_32::ClearInstructionCache() {
     jit.load()->ClearCache();
 }
 
-void ARM_Dynarmic_32::InvalidateCacheRange(VAddr addr, std::size_t size) {
+void ARM_Dynarmic_32::InvalidateCacheRange(u64 addr, std::size_t size) {
     jit.load()->InvalidateCacheRange(static_cast<u32>(addr), size);
 }
 
diff --git a/src/core/arm/dynarmic/arm_dynarmic_32.h b/src/core/arm/dynarmic/arm_dynarmic_32.h
index d24ba2289..bce695daf 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_32.h
+++ b/src/core/arm/dynarmic/arm_dynarmic_32.h
@@ -41,8 +41,8 @@ public:
     void SetVectorReg(int index, u128 value) override;
     u32 GetPSTATE() const override;
     void SetPSTATE(u32 pstate) override;
-    VAddr GetTlsAddress() const override;
-    void SetTlsAddress(VAddr address) override;
+    u64 GetTlsAddress() const override;
+    void SetTlsAddress(u64 address) override;
     void SetTPIDR_EL0(u64 value) override;
     u64 GetTPIDR_EL0() const override;
 
@@ -60,7 +60,7 @@ public:
     void ClearExclusiveState() override;
 
     void ClearInstructionCache() override;
-    void InvalidateCacheRange(VAddr addr, std::size_t size) override;
+    void InvalidateCacheRange(u64 addr, std::size_t size) override;
     void PageTableChanged(Common::PageTable& new_page_table,
                           std::size_t new_address_space_size_in_bits) override;
 
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 7229fdc2a..67073c84d 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -117,7 +117,7 @@ public:
     }
 
     void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
-                                         VAddr value) override {
+                                         u64 value) override {
         switch (op) {
         case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: {
             static constexpr u64 ICACHE_LINE_SIZE = 64;
@@ -199,7 +199,7 @@ public:
         return parent.system.CoreTiming().GetClockTicks();
     }
 
-    bool CheckMemoryAccess(VAddr addr, u64 size, Kernel::DebugWatchpointType type) {
+    bool CheckMemoryAccess(u64 addr, u64 size, Kernel::DebugWatchpointType type) {
         if (!check_memory_access) {
             return true;
         }
@@ -452,7 +452,7 @@ u64 ARM_Dynarmic_64::GetTlsAddress() const {
     return cb->tpidrro_el0;
 }
 
-void ARM_Dynarmic_64::SetTlsAddress(VAddr address) {
+void ARM_Dynarmic_64::SetTlsAddress(u64 address) {
     cb->tpidrro_el0 = address;
 }
 
@@ -500,7 +500,7 @@ void ARM_Dynarmic_64::ClearInstructionCache() {
     jit.load()->ClearCache();
 }
 
-void ARM_Dynarmic_64::InvalidateCacheRange(VAddr addr, std::size_t size) {
+void ARM_Dynarmic_64::InvalidateCacheRange(u64 addr, std::size_t size) {
     jit.load()->InvalidateCacheRange(addr, size);
 }
 
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.h b/src/core/arm/dynarmic/arm_dynarmic_64.h
index ed1a5eb96..e83599e82 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.h
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.h
@@ -38,8 +38,8 @@ public:
     void SetVectorReg(int index, u128 value) override;
     u32 GetPSTATE() const override;
     void SetPSTATE(u32 pstate) override;
-    VAddr GetTlsAddress() const override;
-    void SetTlsAddress(VAddr address) override;
+    u64 GetTlsAddress() const override;
+    void SetTlsAddress(u64 address) override;
     void SetTPIDR_EL0(u64 value) override;
     u64 GetTPIDR_EL0() const override;
 
@@ -53,7 +53,7 @@ public:
     void ClearExclusiveState() override;
 
     void ClearInstructionCache() override;
-    void InvalidateCacheRange(VAddr addr, std::size_t size) override;
+    void InvalidateCacheRange(u64 addr, std::size_t size) override;
     void PageTableChanged(Common::PageTable& new_page_table,
                           std::size_t new_address_space_size_in_bits) override;
 
-- 
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