From 7a27a117706d413af0b677f42d16374b0cb2f82b Mon Sep 17 00:00:00 2001
From: Subv <subv2112@gmail.com>
Date: Mon, 19 Mar 2018 16:49:41 -0500
Subject: GPU: Added Z buffer registers to Maxwell3D's reg structure.

---
 src/video_core/engines/maxwell_3d.h | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index f354241e4..c2db3154a 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -83,7 +83,22 @@ public:
                     }
                 } rt[NumRenderTargets];
 
-                INSERT_PADDING_WORDS(0x207);
+                INSERT_PADDING_WORDS(0x178);
+
+                struct {
+                    u32 address_high;
+                    u32 address_low;
+                    u32 format;
+                    u32 block_dimensions;
+                    u32 layer_stride;
+
+                    GPUVAddr Address() const {
+                        return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
+                                                     address_low);
+                    }
+                } zeta;
+
+                INSERT_PADDING_WORDS(0x8A);
 
                 struct {
                     union {
@@ -321,6 +336,7 @@ private:
                   "Field " #field_name " has invalid position")
 
 ASSERT_REG_POSITION(rt, 0x200);
+ASSERT_REG_POSITION(zeta, 0x3F8);
 ASSERT_REG_POSITION(rt_control, 0x487);
 ASSERT_REG_POSITION(tsc, 0x557);
 ASSERT_REG_POSITION(tic, 0x55D);
-- 
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