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2019-07-11core/arm: Remove obsolete Unicorn memory mappingLioncash1-3/+0
This was initially necessary when AArch64 JIT emulation was in its infancy and all memory-related instructions weren't implemented. Given the JIT now has all of these facilities implemented, we can remove these functions from the CPU interface.
2019-04-12core/cpu_core_manager: Create threads separately from initialization.Lioncash1-1/+1
Our initialization process is a little wonky than one would expect when it comes to code flow. We initialize the CPU last, as opposed to hardware, where the CPU obviously needs to be first, otherwise nothing else would work, and we have code that adds checks to get around this. For example, in the page table setting code, we check to see if the system is turned on before we even notify the CPU instances of a page table switch. This results in dead code (at the moment), because the only time a page table switch will occur is when the system is *not* running, preventing the emulated CPU instances from being notified of a page table switch in a convenient manner (technically the code path could be taken, but we don't emulate the process creation svc handlers yet). This moves the threads creation into its own member function of the core manager and restores a little order (and predictability) to our initialization process. Previously, in the multi-threaded cases, we'd kick off several threads before even the main kernel process was created and ready to execute (gross!). Now the initialization process is like so: Initialization: 1. Timers 2. CPU 3. Kernel 4. Filesystem stuff (kind of gross, but can be amended trivially) 5. Applet stuff (ditto in terms of being kind of gross) 6. Main process (will be moved into the loading step in a following change) 7. Telemetry (this should be initialized last in the future). 8. Services (4 and 5 should ideally be alongside this). 9. GDB (gross. Uses namespace scope state. Needs to be refactored into a class or booted altogether). 10. Renderer 11. GPU (will also have its threads created in a separate step in a following change). Which... isn't *ideal* per-se, however getting rid of the wonky intertwining of CPU state initialization out of this mix gets rid of most of the footguns when it comes to our initialization process.
2019-04-08kernel/svc: Deglobalize the supervisor call handlersLioncash1-6/+6
Adjusts the interface of the wrappers to take a system reference, which allows accessing a system instance without using the global accessors. This also allows getting rid of all global accessors within the supervisor call handling code. While this does make the wrappers themselves slightly more noisy, this will be further cleaned up in a follow-up. This eliminates the global system accessors in the current code while preserving the existing interface.
2019-04-04core: Add missing override specifiers where applicableLioncash1-1/+1
Applies the override specifier where applicable. In the case of destructors that are defaulted in their definition, they can simply be removed. This also removes the unnecessary inclusions being done in audin_u and audrec_u, given their close proximity.
2019-03-15gdbstub: Fix some bugs in IsMemoryBreak() and ServeBreak. Add workaround to let watchpoints break into GDB. (#4651)Dimitri A1-1/+1
* gdbstub: fix IsMemoryBreak() returning false while connected to client As a result, the only existing codepath for a memory watchpoint hit to break into GDB (InterpeterMainLoop, GDB_BP_CHECK, ARMul_State::RecordBreak) is finally taken, which exposes incorrect logic* in both RecordBreak and ServeBreak. * a blank BreakpointAddress structure is passed, which sets r15 (PC) to NULL * gdbstub: DynCom: default-initialize two members/vars used in conditionals * gdbstub: DynCom: don't record memory watchpoint hits via RecordBreak() For now, instead check for GDBStub::IsMemoryBreak() in InterpreterMainLoop and ServeBreak. Fixes PC being set to a stale/unhit breakpoint address (often zero) when a memory watchpoint (rwatch, watch, awatch) is handled in ServeBreak() and generates a GDB trap. Reasons for removing a call to RecordBreak() for memory watchpoints: * The``breakpoint_data`` we pass is typed Execute or None. It describes the predicted next code breakpoint hit relative to PC; * GDBStub::IsMemoryBreak() returns true if a recent Read/Write operation hit a watchpoint. It doesn't specify which in return, nor does it trace it anywhere. Thus, the only data we could give RecordBreak() is a placeholder BreakpointAddress at offset NULL and type Access. I found the idea silly, compared to simply relying on GDBStub::IsMemoryBreak(). There is currently no measure in the code that remembers the addresses (and types) of any watchpoints that were hit by an instruction, in order to send them to GDB as "extended stop information." I'm considering an implementation for this. * gdbstub: Change an ASSERT to DEBUG_ASSERT I have never seen the (Reg[15] == last_bkpt.address) assert fail in practice, even after several weeks of (locally) developping various branches around GDB. Only leave it inside Debug builds.
2019-02-16core_timing: Convert core timing into a classLioncash1-1/+7
Gets rid of the largest set of mutable global state within the core. This also paves a way for eliminating usages of GetInstance() on the System class as a follow-up. Note that no behavioral changes have been made, and this simply extracts the functionality into a class. This also has the benefit of making dependencies on the core timing functionality explicit within the relevant interfaces.
2018-12-19Moved backtrace to ArmInterfaceDavid Marcec1-1/+0
2018-12-03Moved backtrace to ArmInterfaceDavid Marcec1-0/+1
Added to both dynarmic and unicorn
2018-09-18arm_interface: Remove ARM11-isms from the CPU interfaceLioncash1-6/+4
This modifies the CPU interface to more accurately match an AArch64-supporting CPU as opposed to an ARM11 one. Two of the methods don't even make sense to keep around for this interface, as Adv Simd is used, rather than the VFP in the primary execution state. This is essentially a modernization change that should have occurred from the get-go.
2018-09-15Port #4182 from Citra: "Prefix all size_t with std::"fearlessTobi1-2/+2
2018-08-25core: Namespace all code in the arm subdirectory under the Core namespaceLioncash1-0/+4
Gets all of these types and interfaces out of the global namespace.
2018-07-21CPU: Save and restore the TPIDR_EL0 system register on every context switch.Subv1-0/+2
Note that there's currently a dynarmic bug preventing this register from being written.
2018-07-16scheduler: Clear exclusive state when switching contextsMerryMage1-0/+1
2018-06-06GDB Stub Improvements (#508)Hedges1-0/+4
* GDB Stub should work now. * Applied clang-format. * Replaced htonll with swap64. * Tidy up.
2018-03-16arm_interface: Support unmapping previously mapped memory.bunnei1-0/+1
2018-02-25Implements citra-emu/citra#3184N00byKing1-1/+3
2018-01-13yuzu: Update license text to be consistent across project.bunnei1-1/+1
2018-01-12arm_dynarmic: Implement coreMerryMage1-3/+2
2018-01-04unicorn: Use for arm interface on Windows.bunnei1-8/+9
2018-01-04arm_dynarmic: More cleanup.bunnei1-6/+0
2018-01-04arm_dynarmic: Gut interface until dynarmic is ready for general use.bunnei1-8/+3
2018-01-03arm: Remove SkyEye/Dyncom code that is ARMv6-only.bunnei1-6/+1
2017-09-30arm_interface: Set TLS address for dynarmic core.bunnei1-0/+2
2017-09-30arm: Use 64-bit addressing in a bunch of places.bunnei1-4/+4
2017-09-30Moved down_count to CoreTimingHuw Pascoe1-2/+0
2017-09-25ARM_Interface: Implement PageTableChangedMerryMage1-1/+9
2017-02-03arm_dynarmic: CP15 supportMerryMage1-1/+1
2016-12-22ThreadContext: Move from "core" to "arm_interface".bunnei1-6/+2
2016-09-21Remove empty newlines in #include blocks.Emmanuel Gil Peyrot1-3/+0
This makes clang-format useful on those. Also add a bunch of forgotten transitive includes, which otherwise prevented compilation.
2016-09-15arm: ResetContext shouldn't be part of ARM_Interface.bunnei1-1/+0
2016-09-15arm_dynarmic/arm_dyncom: Remove unnecessary "virtual" keyword.bunnei1-1/+1
2016-09-15dynarmic: Implement ARM CPU interface.bunnei1-8/+9
2016-08-27ARM: add ClearInstructionCache functionwwylele1-0/+2
2015-08-07arm_interface: Implement interface for retrieving VFP registersLioncash1-0/+4
2015-07-26dyncom: Rename armdefs.h to armstate.hLioncash1-1/+1
2015-06-28Core: Cleanup core includes.Emmanuel Gil Peyrot1-0/+5
2015-05-11fixup! Set the TLS address in the schedulerSubv1-1/+1
2015-05-11Core/Memory: Give every emulated thread it's own TLS area.Subv1-1/+1
The TLS area for thread T with id Ti is located at TLS_AREA_VADDR + (Ti - 1) * 0x200. This allows some games like Mario Kart 7 to continue further.
2015-04-14Headers: Add some forgotten overrides, thanks clang!Emmanuel Gil Peyrot1-1/+1
2015-04-06arm_interface: Support retrieval/storage to CP15 registersLioncash1-0/+2
2015-03-16arm_interface: Get rid of GetTicks.Lioncash1-1/+0
Removes a TODO.
2015-02-13dyncom: Switch the app and system cores into the correct mode at initializationLioncash1-1/+1
2015-02-10Scheduler refactor Pt. 1Kevin Hartman1-56/+1
* Simplifies scheduling logic, specifically regarding thread status. It should be much clearer which statuses are valid for a thread at any given point in the system. * Removes dead code from thread.cpp. * Moves the implementation of resetting a ThreadContext to the corresponding core's implementation. Other changes: * Fixed comments in arm interfaces. * Updated comments in thread.cpp * Removed confusing, useless, functions like MakeReady() and ChangeStatus() from thread.cpp. * Removed stack_size from Thread. In the CTR kernel, the thread's stack would be allocated before thread creation.
2015-01-09Move ThreadContext to core/core.h and deal with the falloutYuri Kunde Schlesner1-2/+2
2015-01-09Timing: Use CoreTiming::GetTicks to keep track of ticks.Subv1-3/+0
This will keep track of idle ticks for us, and fixes some tickcount-related issues
2014-12-26ARM: Add a mechanism for faking CPU time elapsed during HLE.bunnei1-4/+10
- Also a few cleanups.
2014-12-21License changepurpasmart961-1/+1
2014-11-19Remove trailing spaces in every file but the ones imported from SkyEye, AOSP or generatedEmmanuel Gil Peyrot1-1/+1
2014-11-18Fix documentation of parametersLioncash1-1/+1
2014-10-26Add `override` keyword through the code.Yuri Kunde Schlesner1-7/+7
This was automated using `clang-modernize`.
2014-10-25ARM: Integrate SkyEye faster "dyncom" interpreter.bunnei1-8/+8
Fixed typo (make protected member public) Added license header back in. I originally removed this because I mostly rewrote the file, but meh ARM: Fixed a type error in dyncom interpreter. ARM: Updated dyncom to use unique_ptr for internal ARM state.
2014-10-25ARM: Reorganized file structure to move shared SkyEye code to a more common area.bunnei1-2/+2
Removed s_ prefix
2014-06-02arm: added option to prepare CPU core (while mid-instruction) for thread reschedulebunnei1-0/+3
2014-05-21ARM_Interpreter/ARM_Interface: Fixed member variable naming to be consistent with style guidebunnei1-1/+1
2014-05-21ARM_Interface: added SaveContext and LoadContext functions for HLE thread switchingbunnei1-0/+12
2014-05-17updated how we call ARM core to make things much fasterbunnei1-2/+5
2014-05-12added option to set CPSR register to arm_interfacebunnei1-0/+6
2014-04-28removed DISALLOW_COPY_AND_ASSIGN in favor of NonCopyable classbunnei1-1/+0
2014-04-11cleaned up arm_interface, added a setter to set registers for use with HLE return valuesbunnei1-2/+35
2014-04-09fixed licensing and updated code style naming for arm_interface/arm_interpreter frontend modulebunnei1-30/+8
2014-04-09fixed project includes to use new directory structurebunnei1-5/+4
2014-04-09got rid of 'src' folders in each sub-projectbunnei1-0/+0
2014-04-05changed hw_lcd to use ARM core correct tick counter instead of [what was actually] just an instruction count. this seems to fix timing issues with the 3DS_Homebrew_Pong3Dv2 demo.bunnei1-0/+7
2014-04-05- added an interface layer for ARM coresbunnei1-28/+21
- cleaned up core.cpp a bit
2013-10-06fixed a typo in declaration of meta file systemShizZy1-2/+2
2013-10-03moved some core functions over to system moduleShizZy1-1/+6
2013-10-02added core_timing and system modules to core vcprojShizZy1-0/+52