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* arm: dynarmic: Reintroduce JIT checks on SaveContext/LoadContext.bunnei2021-01-292-0/+12
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* core: arm: Remove unnecessary JIT checks.bunnei2021-01-292-24/+0
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* arm: arm_dynarmic: Skip calls when JIT is invalid.bunnei2021-01-292-0/+24
| | | | - This can happen if called from an idle or suspension thread.
* core: Silence unhandled enum in switch warningsReinUsesLisp2021-01-091-8/+1
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* dynarmic: Add Unsafe_InaccurateNaN optimizationMerryMage2021-01-022-0/+6
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* core/memory: Read and write page table atomicallyReinUsesLisp2020-12-302-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Squash attributes into the pointer's integer, making them an uintptr_t pair containing 2 bits at the bottom and then the pointer. These bits are currently unused thanks to alignment requirements. Configure Dynarmic to mask out these bits on pointer reads. While we are at it, remove some unused attributes carried over from Citra. Read/Write and other hot functions use a two step unpacking process that is less readable to stop MSVC from emitting an extra AND instruction in the hot path: mov rdi,rcx shr rdx,0Ch mov r8,qword ptr [rax+8] mov rax,qword ptr [r8+rdx*8] mov rdx,rax -and al,3 and rdx,0FFFFFFFFFFFFFFFCh je Core::Memory::Memory::Impl::Read<unsigned char> mov rax,qword ptr [vaddr] movzx eax,byte ptr [rdx+rax]
* hle: kernel: Rewrite scheduler implementation based on Mesopshere.bunnei2020-12-061-1/+1
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* hle: kernel: physical_core: Clear exclusive state after each run.bunnei2020-12-062-0/+6
| | | | - This is closer to pre-multicore behavior, and works a bit better.
* core: arm: Implement InvalidateCacheRange for CPU cache invalidation.bunnei2020-11-294-0/+16
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* hle: kernel: multicore: Replace n-JITs impl. with 4 JITs.bunnei2020-11-294-0/+10
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* core: Eliminate remaining usages of the global system instanceLioncash2020-11-271-11/+0
| | | | | | Removes all remaining usages of the global system instance. After this, migration can begin to migrate to being constructed and managed entirely by the various frontends.
* core: Remove usage of unicornLioncash2020-11-043-23/+9
| | | | | | | | Unicorn long-since lost most of its use, due to dynarmic gaining support for handling most instructions. At this point any further issues encountered should be used to make dynarmic better. This also allows us to remove our dependency on Python.
* Revert "core: Fix clang build"bunnei2020-10-214-18/+18
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* core: Fix clang buildLioncash2020-10-184-18/+18
| | | | | | | Recent changes to the build system that made more warnings be flagged as errors caused building via clang to break. Fixes #4795
* General: Make use of std::nullopt where applicableLioncash2020-09-221-3/+3
| | | | | | | | Allows some implementations to avoid completely zeroing out the internal buffer of the optional, and instead only set the validity byte within the structure. This also makes it consistent how we return empty optionals.
* arm_dynarmic_cp15: Initialize member variablesLioncash2020-09-171-2/+2
| | | | | Ensures that the member variables are always initialized to a deterministic value on creation.
* dynarmic: Add unsafe optimizationsMerryMage2020-08-162-2/+24
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* configure_cpu: Show/Hide debugging optionsMerryMage2020-07-112-46/+50
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* configuration: Add settings to enable/disable specific CPU optimizationsMerryMage2020-07-112-10/+50
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* Core/Common: Address Feedback.Fernando Sahmkow2020-06-284-6/+8
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* SVC: Implement 32-bits wrappers and update Dynarmic.Fernando Sahmkow2020-06-271-1/+7
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* ARM: Update Dynarmic and Setup A32 according to latest interface.Fernando Sahmkow2020-06-276-92/+165
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* ArmDynarmic32: Setup CNTPCT correctlyFernando Sahmkow2020-06-271-1/+1
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* ARMDynarmicInterface: Correct GCC Build Errors.Fernando Sahmkow2020-06-272-6/+6
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* ARMInterface/Externals: Update dynarmic and fit to latest version.Fernando Sahmkow2020-06-271-7/+7
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* ARMInterface: Correct rebase errors.Fernando Sahmkow2020-06-271-2/+2
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* Dynarmic Interface: don't clear cache if JIT has not been created.Fernando Sahmkow2020-06-272-0/+6
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* General: Cleanup legacy code.Fernando Sahmkow2020-06-272-2/+0
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* SingleCore: Use Cycle Timing instead of Host Timing.Fernando Sahmkow2020-06-274-27/+53
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* General: Move ARM_Interface into Threads.Fernando Sahmkow2020-06-274-0/+10
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* Core: Refactor ARM Interface.Fernando Sahmkow2020-06-274-10/+13
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* X64 Clock: Reduce accuracy to be less or equal to guest accuracy.Fernando Sahmkow2020-06-271-0/+3
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* SVC/ARM: Correct svcSendSyncRequest and cache ticks on arm interface.Fernando Sahmkow2020-06-272-4/+19
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* ARM: Addapt to new Exclusive Monitor Interface.Fernando Sahmkow2020-06-272-17/+15
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* General: Fix microprofile on dynarmic/svc, fix wait tree showing which threads were running.Fernando Sahmkow2020-06-272-8/+1
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* ARM/Memory: Correct Exclusive Monitor and Implement Exclusive Memory Writes.Fernando Sahmkow2020-06-272-14/+58
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* Core: Correct rebase.Fernando Sahmkow2020-06-271-12/+6
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* General: Recover Prometheus project from harddrive failure Fernando Sahmkow2020-06-274-22/+20
| | | | | | | This commit: Implements CPU Interrupts, Replaces Cycle Timing for Host Timing, Reworks the Kernel's Scheduler, Introduce Idle State and Suspended State, Recreates the bootmanager, Initializes Multicore system.
* arm_dynarmic_64: Log the instruction when an exception is raisedMorph2020-06-221-2/+2
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* arm_dynarmic_32: Log under Core_ARM instead of HW_GPUMorph2020-06-221-1/+1
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* arm_dynarmic_32: Fix implicit conversion error in SetTPIDR_EL0ReinUsesLisp2020-06-181-1/+1
| | | | On MSVC builds we treat conversion warnings as errors.
* arm_dynarmic_cp15: Implement CNTPCTMerryMage2020-06-171-0/+13
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* arm_dynarmic_cp15: Update CP15MerryMage2020-06-174-142/+73
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* arm_dynarmic_32: InterpreterFallback should never happenMerryMage2020-06-171-2/+3
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* physical_core: Make use of std::make_unique instead of std::make_shared in ctorLioncash2020-04-241-4/+3
| | | | | | | We can also allow unicorn to be constructed in 32-bit mode or 64-bit mode to satisfy the need for both interpreter instances. Allows this code to compile successfully of non x86-64 architectures.
* dynarmic: Add option to disable CPU JIT optimizationsMerryMage2020-04-201-2/+8
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* dynarmic: Enable strict alignment checks.bunnei2020-04-171-1/+4
| | | | - Also add a missing include.
* core: memory: Move to Core::Memory namespace.bunnei2020-04-172-3/+3
| | | | - helpful to disambiguate Kernel::Memory namespace.
* core: kernel: Move SVC to its own namesapce.bunnei2020-04-172-2/+2
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* core: Implement separate A32/A64 ARM interfaces.bunnei2020-03-034-51/+338
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* core: dynarmic: Add CP15 from Citra.bunnei2020-03-032-0/+232
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* ARM_Interface: Cache the JITs instead of deleting/recreating.Fernando Sahmkow2020-02-262-4/+19
| | | | | | This was a bug inherited from citra which was fixed by then at some time. This commit corrects such bug and ensures JITs are correctly recycled.
* Core: Set all hardware emulation constants in a single file.Fernando Sahmkow2020-02-121-1/+2
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* core/arm: Remove usage of global GetCurrentThread()Lioncash2020-01-311-1/+2
| | | | | Now both CPU backends go through their referenced system instance to obtain the current thread.
* Core: Refactor CpuCoreManager to CpuManager and Cpu to Core Manager.Fernando Sahmkow2020-01-261-1/+1
| | | | This commit instends on better naming the new purpose of this classes.
* core/memory + arm/dynarmic: Use a global offset within our arm page table.Markus Wick2020-01-011-0/+1
| | | | | | This saves us two x64 instructions per load/store instruction. TODO: Clean up our memory code. We can use this optimization here as well.
* core/memory: Migrate over Write{8, 16, 32, 64, Block} to the Memory classLioncash2019-11-272-15/+22
| | | | | | | | | The Write functions are used slightly less than the Read functions, which make these a bit nicer to move over. The only adjustments we really need to make here are to Dynarmic's exclusive monitor instance. We need to keep a reference to the currently active memory instance to perform exclusive read/write operations.
* core/memory: Migrate over Read{8, 16, 32, 64, Block} to the Memory classLioncash2019-11-271-6/+6
| | | | | | | | | | | | | | With all of the trivial parts of the memory interface moved over, we can get right into moving over the bits that are used. Note that this does require the use of GetInstance from the global system instance to be used within hle_ipc.cpp and the gdbstub. This is fine for the time being, as they both already rely on the global system instance in other functions. These will be removed in a change directed at both of these respectively. For now, it's sufficient, as it still accomplishes the goal of de-globalizing the memory code.
* core: Prepare various classes for memory read/write migrationLioncash2019-11-272-4/+5
| | | | | | | | | | Amends a few interfaces to be able to handle the migration over to the new Memory class by passing the class by reference as a function parameter where necessary. Notably, within the filesystem services, this eliminates two ReadBlock() calls by using the helper functions of HLERequestContext to do that for us.
* arm_unicorn: Resolve sign conversion warningsLioncash2019-11-121-1/+1
| | | | | While we're at it, this also resolves a type truncation warning as well, given the code was truncating from a 64-bit value to a 32-bit one.
* Core_Timing: Address Feedback and suppress warnings.Fernando Sahmkow2019-10-111-1/+1
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* Core Timing: Rework Core Timing to run all cores evenly.Fernando Sahmkow2019-10-091-1/+1
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* Revert "arm_dynarmic: Check if jit is nullptr when preparing reschedule"bunnei2019-09-301-3/+0
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* Merge pull request #2574 from DarkLordZach/dynarmic-jit-nullptrbunnei2019-09-301-0/+3
|\ | | | | arm_dynarmic: Check if jit is nullptr when preparing reschedule
| * arm_dynarmic: Check if jit is nullptr when preparing rescheduleZach Hilman2019-06-101-0/+3
| | | | | | | | Prevents crash with multiprocess loading.
* | core/arm: Remove obsolete Unicorn memory mappingLioncash2019-07-112-12/+0
|/ | | | | | | | This was initially necessary when AArch64 JIT emulation was in its infancy and all memory-related instructions weren't implemented. Given the JIT now has all of these facilities implemented, we can remove these functions from the CPU interface.
* core/cpu_core_manager: Create threads separately from initialization.Lioncash2019-04-122-17/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Our initialization process is a little wonky than one would expect when it comes to code flow. We initialize the CPU last, as opposed to hardware, where the CPU obviously needs to be first, otherwise nothing else would work, and we have code that adds checks to get around this. For example, in the page table setting code, we check to see if the system is turned on before we even notify the CPU instances of a page table switch. This results in dead code (at the moment), because the only time a page table switch will occur is when the system is *not* running, preventing the emulated CPU instances from being notified of a page table switch in a convenient manner (technically the code path could be taken, but we don't emulate the process creation svc handlers yet). This moves the threads creation into its own member function of the core manager and restores a little order (and predictability) to our initialization process. Previously, in the multi-threaded cases, we'd kick off several threads before even the main kernel process was created and ready to execute (gross!). Now the initialization process is like so: Initialization: 1. Timers 2. CPU 3. Kernel 4. Filesystem stuff (kind of gross, but can be amended trivially) 5. Applet stuff (ditto in terms of being kind of gross) 6. Main process (will be moved into the loading step in a following change) 7. Telemetry (this should be initialized last in the future). 8. Services (4 and 5 should ideally be alongside this). 9. GDB (gross. Uses namespace scope state. Needs to be refactored into a class or booted altogether). 10. Renderer 11. GPU (will also have its threads created in a separate step in a following change). Which... isn't *ideal* per-se, however getting rid of the wonky intertwining of CPU state initialization out of this mix gets rid of most of the footguns when it comes to our initialization process.
* kernel/svc: Deglobalize the supervisor call handlersLioncash2019-04-082-15/+12
| | | | | | | | | | | Adjusts the interface of the wrappers to take a system reference, which allows accessing a system instance without using the global accessors. This also allows getting rid of all global accessors within the supervisor call handling code. While this does make the wrappers themselves slightly more noisy, this will be further cleaned up in a follow-up. This eliminates the global system accessors in the current code while preserving the existing interface.
* arm/arm_dynarmic: Remove unnecessary current_page_table memberLioncash2019-04-072-8/+0
| | | | | Given the page table will always be guaranteed to be that of whatever the current process is, we no longer need to keep this around.
* core: Add missing override specifiers where applicableLioncash2019-04-042-3/+2
| | | | | | | | | Applies the override specifier where applicable. In the case of destructors that are defaulted in their definition, they can simply be removed. This also removes the unnecessary inclusions being done in audin_u and audrec_u, given their close proximity.
* core: Move PageTable struct into Common.bunnei2019-03-171-2/+2
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* Corrections, documenting and fixes.Fernando Sahmkow2019-02-161-1/+1
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* Use u128 on Clock Cycles calculation.Fernando Sahmkow2019-02-161-1/+1
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* Correct CNTPCT to use Clock Cycles instead of Cpu Cycles.Fernando Sahmkow2019-02-161-2/+3
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* core_timing: Convert core timing into a classLioncash2019-02-162-6/+14
| | | | | | | | | | | Gets rid of the largest set of mutable global state within the core. This also paves a way for eliminating usages of GetInstance() on the System class as a follow-up. Note that no behavioral changes have been made, and this simply extracts the functionality into a class. This also has the benefit of making dependencies on the core timing functionality explicit within the relevant interfaces.
* core_timing: Rename CoreTiming namespace to Core::TimingLioncash2019-02-121-3/+3
| | | | | | Places all of the timing-related functionality under the existing Core namespace to keep things consistent, rather than having the timing utilities sitting in its own completely separate namespace.
* arm_dynarmic: Set CNTFRQ valueMerryMage2018-12-181-0/+1
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* core: Make the exclusive monitor a unique_ptr instead of a shared_ptrLioncash2018-10-152-6/+5
| | | | | | Like the barrier, this is owned entirely by the System and will always outlive the encompassing state, so shared ownership semantics aren't necessary here.
* kernel/thread: Use a regular pointer for the owner/current processLioncash2018-10-101-1/+1
| | | | | | | | | | | There's no real need to use a shared pointer in these cases, and only makes object management more fragile in terms of how easy it would be to introduce cycles. Instead, just do the simple thing of using a regular pointer. Much of this is just a hold-over from citra anyways. It also doesn't make sense from a behavioral point of view for a process' thread to prolong the lifetime of the process itself (the process is supposed to own the thread, not the other way around).
* kernel/thread: Make all instance variables privateLioncash2018-10-041-1/+1
| | | | | | | | | | | | | | | | | | | | Many of the member variables of the thread class aren't even used outside of the class itself, so there's no need to make those variables public. This change follows in the steps of the previous changes that made other kernel types' members private. The main motivation behind this is that the Thread class will likely change in the future as emulation becomes more accurate, and letting random bits of the emulator access data members of the Thread class directly makes it a pain to shuffle around and/or modify internals. Having all data members public like this also makes it difficult to reason about certain bits of behavior without first verifying what parts of the core actually use them. Everything being public also generally follows the tendency for changes to be introduced in completely different translation units that would otherwise be better introduced as an addition to the Thread class' public interface.
* kernel/process: Make data member variables privateLioncash2018-09-301-2/+2
| | | | | | | Makes the public interface consistent in terms of how accesses are done on a process object. It also makes it slightly nicer to reason about the logic of the process class, as we don't want to expose everything to external code.
* arm_interface: Add missing fpsr/tpidr members to the ThreadContext structLioncash2018-09-301-2/+6
| | | | | | | | | Internally within the kernel, it also includes a member variable for the floating-point status register, and TPIDR, so we should do the same here to match it. While we're at it, also fix up the size of the struct and add a static assertion to ensure it always stays the correct size.
* Merge pull request #1395 from lioncash/vmbunnei2018-09-291-2/+3
|\ | | | | process/vm_manager: Initial modifications to load NPDM metadata
| * memory: Dehardcode the use of a 36-bit address spaceLioncash2018-09-251-2/+3
| | | | | | | | | | Given games can also request a 32-bit or 39-bit address space, we shouldn't be hardcoding the address space range as 36-bit.
* | FPCR register was uninitialized at start upPhilippe Babin2018-09-231-1/+1
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* arm_interface: Replace kernel vm_manager include with a forward declarationLioncash2018-09-212-0/+5
| | | | | | Avoids an unnecessary inclusion and also uncovers three places where indirect inclusions were relied upon, which allows us to also resolve those.
* arm_dynarmic: Halt when BRK encounteredMerryMage2018-09-201-0/+1
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* arm_dynarmic: Support BKPT instructionMerryMage2018-09-191-0/+11
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* Merge pull request #1344 from lioncash/armbunnei2018-09-182-26/+15
|\ | | | | arm_interface: Remove ARM11-isms from the CPU interface
| * arm_interface: Remove ARM11-isms from the CPU interfaceLioncash2018-09-182-26/+15
| | | | | | | | | | | | | | | | | | This modifies the CPU interface to more accurately match an AArch64-supporting CPU as opposed to an ARM11 one. Two of the methods don't even make sense to keep around for this interface, as Adv Simd is used, rather than the VFP in the primary execution state. This is essentially a modernization change that should have occurred from the get-go.
* | arm_dynarmic: Correct ExclusiveWrite128()'s operationLioncash2018-09-181-2/+2
|/ | | | | | Previously the second half of the value being written would overwrite the first half. Thankfully this wasn't a bug that was being encountered, as the function is currently unused.
* Port #4182 from Citra: "Prefix all size_t with std::"fearlessTobi2018-09-152-24/+25
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* Update microprofile scopes.Markus Wick2018-09-041-0/+4
| | | | | | Blame the subsystems which deserve the blame :) The updated list is not complete, just the ones I've spotted on random sampling the stack trace.
* core/core: Replace includes with forward declarations where applicableLioncash2018-08-311-0/+1
| | | | | | | | | | | The follow-up to e2457418dae19b889b2ad85255bb95d4cd0e4bff, which replaces most of the includes in the core header with forward declarations. This makes it so that if any of the headers the core header was previously including change, then no one will need to rebuild the bulk of the core, due to core.h being quite a prevalent inclusion. This should make turnaround for changes much faster for developers.
* core: Namespace all code in the arm subdirectory under the Core namespaceLioncash2018-08-252-0/+8
| | | | Gets all of these types and interfaces out of the global namespace.
* dynarmic: Update to 550d662MerryMage2018-08-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | 550d662 load_store_exclusive: Define s == t state to be Constraint_NONE 0b69381 A64/translate: Allow for unpredictable behaviour to be defined 6d236d4 system: Implement MRS CNTFRQ_EL0 6cbb6fb A32/testenv: Add missing headers 6729328 externals: Update xbyak to v5.67 1812bd2 Squashed 'externals/xbyak/' changes from 2794cde7..671fc805 9a95802 externals: Document subtrees 714a840 A64: Implement SQ{ADD, SUB}, and UQ{ADD, SUB}'s vector variants 8cab459 A64: Implement UQADD/UQSUB's scalar variants 18a8151 ir: Add opcodes for unsigned saturating add and subtract a5660ee x64/reg_alloc: Use type alias for array returned by GetArgumentInfo() 29489b5 ir/value: Use type alias CoprocessorInfo for std::array<u8, 8> e23ba26 status_register_access: Add support for bits 0 and 1 of mask to MSR 55190bd fuzz_with_unicorn: Split utility functions into fuzz_util 23b049d A32/translate/load_store: Correct detection of writeback 7ec9f15 A32/translate: Add TranslateSingleInstruction efeecb4 A32/ir_emitter: Bug fix: IREmitter::ExceptionRaised using incorrect opcode 08d1d19 A32/decoders: Split instruction list into include file 2d929cc tests: Refactor unicorn_emu to allow for A32 unicorn f672368 microinstruction: Improve assert messages 7ebff50 emit_x64_vector: EmitVectorNarrow16: AVX512 implementation edce230 emit_x64_vector: EmitVectorNarrow32: prefer pblendw to loading constant
* arm_dynarmic: Remove IsExecuting check from PrepareRescheduleMerryMage2018-08-131-3/+1
| | | | No longer required. HaltExecution is a no-op if it is not currently executing.
* CPU/Timing: Use an approximated amortized amount of ticks when advancing timing.Subv2018-08-131-1/+10
| | | | | | | | We divide the number of ticks to add by the number of cores (4) to obtain a more or less rough estimate of the actual number of ticks added. This assumes that all 4 cores are doing similar work. Previously we were adding ~4 times the number of ticks, thus making the games think that time was going way too fast. This lets us bypass certain hangs in some games like Breath of the Wild. We should modify our CoreTiming to support multiple cores (both running in a single thread, and in multiple host threads).
* Merge pull request #876 from lioncash/includebunnei2018-08-011-1/+1
|\ | | | | kernel: Remove unnecessary includes
| * kernel: Remove unnecessary includesLioncash2018-07-311-1/+1
| | | | | | | | | | Removes unnecessary direct dependencies in some headers and also gets rid of indirect dependencies that were being relied on to be included.
* | arm_dynarmic: Make SetTlsAddress() prototype and definition consistentLioncash2018-07-311-1/+1
| | | | | | | | Makes the definition use the same type aliases as in its prototype.
* | arm_dynarmic: Remove unnecessary qualifying of ThreadContextLioncash2018-07-311-3/+3
| | | | | | | | | | Given the ARM_Dynarmic class inherits from ARM_Interface, we don't need to qualify here.
* | arm_dynarmic: Correct initializer list orderLioncash2018-07-311-5/+3
|/ | | | | | | | | Amends the initializer list to be in the same order that each variable would be initialized in. We also do this to ensure we don't use a bogus uninitialized instance of the exclusive monitor within MakeJit() We can also remove the jit member from the initializer list as this is initialized by PageTableChanged()
* arm_dynarmic: Make MakeJit() a const member functionLioncash2018-07-242-3/+3
| | | | | This functions doesn't modify instance state, so it can be a made a const member function.
* exclusive_monitor: Use consistent type alias for u64Lioncash2018-07-242-14/+12
| | | | | Uses the same type aliases we use for virtual addresses, and converts one lingering usage of std::array<uint64_t, 2> to u128 for consistency.
* Implement exclusive monitorMerryMage2018-07-222-8/+89
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* Merge pull request #750 from lioncash/ctxbunnei2018-07-211-2/+0
|\ | | | | arm_interface: Remove unused tls_address member of ThreadContext
| * arm_interface: Remove unused tls_address member of ThreadContextLioncash2018-07-211-2/+0
| | | | | | | | | | Currently, the TLS address is set within the scheduler, making this member unused.
* | CPU: Save and restore the TPIDR_EL0 system register on every context switch.Subv2018-07-212-0/+10
|/ | | | Note that there's currently a dynarmic bug preventing this register from being written.
* scheduler: Clear exclusive state when switching contextsMerryMage2018-07-162-0/+5
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* Update clang formatJames Rowe2018-07-031-1/+1
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* Rename logging macro back to LOG_*James Rowe2018-07-031-1/+1
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* general: Make formatting of logged hex values more straightforwardLioncash2018-05-021-1/+1
| | | | | | This makes the formatting expectations more obvious (e.g. any zero padding specified is padding that's entirely dedicated to the value being printed, not any pretty-printing that also gets tacked on).
* general: Convert assertion macros over to be fmt-compatibleLioncash2018-04-271-1/+1
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* core: Replace remaining old non-generic logger usages with fmt-capable equivalentsLioncash2018-04-261-2/+2
| | | | | | LOG_GENERIC usages will be amended in a follow-up to keep API changes separate from interface changes, as it will require removing a parameter from the relevant function in the VMManager class.
* arm_dynarmic: Fix timingMerryMage2018-03-241-7/+3
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* Merge pull request #193 from N00byKing/3184_2_robotic_boogaloobunnei2018-03-192-8/+16
|\ | | | | Implement Pull #3184 from citra: core/arm: Improve timing accuracy before service calls in JIT (Rebased)
| * Implements citra-emu/citra#3184N00byKing2018-02-252-8/+16
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* | arm_interface: Support unmapping previously mapped memory.bunnei2018-03-162-1/+5
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* | core: Move process creation out of global state.bunnei2018-03-141-1/+2
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* | dynarmic: Update to 6b4c6b0MerryMage2018-02-211-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 6b4c6b0 impl: Update PC when raising exception 7a1313a A64: Implement FDIV (vector) b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL b277bf5 Correct FPSR and FPCR 7673933 A64: Implement USHL 8d0e558 A64: Implement UCVTF (vector, integer), scalar variant da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 7479684 A64: Implement system register TPIDR_EL0 0fd75fd A64: Implement system registers FPCR and FPSR 31e370c A64: Implement system register CNTPCT_EL0 9a88fd3 A64: Implement system register CTR_EL0 1d16896 A64: Implement NEG (vector) 3184edf IR: Add IR instruction ZeroVector 31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter 567eb1a A64: Implement FMINNM (scalar) c6d8fa1 A64: Implement FMAXNM (scalar) 616056d constant_pool: Add frame parameter a3747cb A64: Implement ADDP (scalar) 5cd5d9f reg_alloc: Only exchange GPRs dd0452a A64: Implement DUP (element), scalar variant e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0 40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar) 7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect 826dce2 travis: Switch unicorn repository 9605f28 a64/config: Allow NaN emulation accuracy to be set e9435bc a64_emit_x64: Add conf to A64EmitContext 30b596d fuzz_with_unicorn: Explicitly test floating point instructions be292a8 A64: Implement FSQRT (scalar) 3c42d48 backend_x64: Accurately handle NaNs 4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
* | arm_dynarmic: LOG_INFO on unicorn fallbackMerryMage2018-02-211-0/+4
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* arm_dynarmic: Support direct page table accessMerryMage2018-02-121-6/+14
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* dynarmic: Update to 41ae12263MerryMage2018-02-092-31/+45
| | | | Changes: Primarily implementing more A64 instructions
* Fixes some cast warnings, partial port of citra #3064 (#106)River City Ransomware2018-01-201-3/+3
| | | | | | | | * Fixes some cast warnings, partially fixes citra #3064 * Converted casts to uint32_t to u32 * Ran clang-format
* Update dynarmic to bc73004MerryMage2018-01-131-12/+17
| | | | | | | | | | | | | | | | | | bc73004 a64_merge_interpret_blocks: Remove debug output 4e656ed tests/A64: Randomize PSTATE.<NZCV> fd9530b A64: Optimization: Merge interpret blocks 3c9eb04 testenv: Use format constants 324f3fc tests/A64: Unicorn interface fixes 98ecbe7 tests/A64: Fuzz against unicorn b1d38e7 tests/A64: Move TestEnvironment to own header 5218ad9 A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate b1a8c39 A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31 64827fb a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers 1bfa04d emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64 edadeea A64 inferface: Use two argument static_assert 9ab1304 A64: Add ExceptionRaised IR instruction 6843eed Update readme 7438d07 A64/translate: Add TranslateSingleInstruction function
* yuzu: Update license text to be consistent across project.bunnei2018-01-132-2/+2
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* arm_dynarmic: Implement coreMerryMage2018-01-122-44/+142
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* arm_dynarmic: More cleanup.bunnei2018-01-041-6/+0
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* arm_dynarmic: Gut interface until dynarmic is ready for general use.bunnei2018-01-042-142/+44
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* arm: Remove SkyEye/Dyncom code that is ARMv6-only.bunnei2018-01-034-147/+6
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* Merge remote-tracking branch 'upstream/master' into nxbunnei2017-10-102-62/+48
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | # Conflicts: # src/core/CMakeLists.txt # src/core/arm/dynarmic/arm_dynarmic.cpp # src/core/arm/dyncom/arm_dyncom.cpp # src/core/hle/kernel/process.cpp # src/core/hle/kernel/thread.cpp # src/core/hle/kernel/thread.h # src/core/hle/kernel/vm_manager.cpp # src/core/loader/3dsx.cpp # src/core/loader/elf.cpp # src/core/loader/ncch.cpp # src/core/memory.cpp # src/core/memory.h # src/core/memory_setup.h
| * Moved down_count to CoreTimingHuw Pascoe2017-09-302-10/+1
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| * ARM_Interface: Implement PageTableChangedMerryMage2017-09-252-6/+26
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| * Merge pull request #2842 from Subv/switchable_page_tableB3n302017-09-151-1/+3
| |\ | | | | | | Kernel/Memory: Give each process its own page table and allow switching the current page table upon reschedule
| | * CPU/Dynarmic: Disable the fast page-table access in dynarmic until it supports switching page tables at runtime.Subv2017-09-151-1/+3
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| * | CPU/Dynarmic: Fixed a warning when incrementing the number of ticks in ExecuteInstructions.Subv2017-08-211-1/+1
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* | arm_interface: Set TLS address for dynarmic core.bunnei2017-09-302-0/+16
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* | arm: Use 64-bit addressing in a bunch of places.bunnei2017-09-302-52/+85
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* arm_dynarmic: Update memory interfaceMerryMage2017-02-031-10/+10
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* arm_dynarmic: CP15 supportMerryMage2017-02-034-5/+128
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* Merge pull request #2366 from MerryMage/MemoryReadCodebunnei2016-12-221-0/+1
|\ | | | | arm_dynarmic: Provide MemoryReadCode callback
| * arm_dynarmic: Provide MemoryReadCode callbackMerryMage2016-12-221-0/+1
| | | | | | | | Change of interface in dynarmic 36082087ded632079b16d24137fdd0c450ce82ea
* | ThreadContext: Move from "core" to "arm_interface".bunnei2016-12-222-8/+4
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* Core: Add a forgotten #include <cstring> for memcpy.Emmanuel Gil Peyrot2016-12-111-0/+1
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* dynarmic: Add ticks based on ticks executed, not ticks requestedMerryMage2016-11-261-2/+2
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* Expose page table to dynarmic for optimized reads and writes to the JITJames Rowe2016-11-251-0/+1
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* Use negative priorities to avoid special-casing the self-includeYuri Kunde Schlesner2016-09-211-1/+1
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* Remove empty newlines in #include blocks.Emmanuel Gil Peyrot2016-09-212-7/+2
| | | | | | | This makes clang-format useful on those. Also add a bunch of forgotten transitive includes, which otherwise prevented compilation.
* arm_dynarmic: Implement GetVFPSystemReg/SetVFPSystemReg.bunnei2016-09-151-5/+12
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* arm: ResetContext shouldn't be part of ARM_Interface.bunnei2016-09-152-10/+0
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* arm_dynarmic/arm_dyncom: Remove unnecessary "virtual" keyword.bunnei2016-09-151-1/+1
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* dynarmic: Implement ARM CPU interface.bunnei2016-09-152-0/+227
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