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* externals: Update dynarmic to HEADLioncash2018-04-201-0/+0
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* dynarmic: Update to 9cc12d8MerryMage2018-03-291-0/+0
| | | | | | 9cc12d8 abi: Missing includes ac35ad5 emit_x64_floating_point: Near jump instead of short jump in FPMinNumberic{32,64} 6f03fdd A64: system: Use an enum class for MRS/MSR register encodings
* dynarmic: Update to 12a1020MerryMage2018-03-271-0/+0
| | | | | | | | | | | | | | | 12a1020 emit_X64_floating_point: Near jmp to end instead of short jmp 6278f83 emit_x64_vector: Fix typo in VectorShuffleImpl 25a0204 A64: Implement REV64 aa92e33 bit_util: Do nothing in RotateRight if the rotation amount is zero e537985 A64: Implement REV32 (vector) f62a258 ir: Add IR opcodes for emitting vector shuffles 36ac6ec emit_x64_vector_floating_point: Fix out of bounds array access in EmitVectorOperation64 20a59a9 A64: Implement REV16 (vector) b2f7bb0 CMakeLists: Add fp_util, macro_util and math_util headers fd21b58 A64: Implement EOR3 and BCAX a48c0bb travis: Use yuzu's unicorn fork 59e62e0 externals: Update catch to v2.2.1
* dynarmic: Update to 6b4c6b0MerryMage2018-02-211-0/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 6b4c6b0 impl: Update PC when raising exception 7a1313a A64: Implement FDIV (vector) b2d781d system: Raise exception for YIELD, WFE, WFI, SEV, SEVL b277bf5 Correct FPSR and FPCR 7673933 A64: Implement USHL 8d0e558 A64: Implement UCVTF (vector, integer), scalar variant da9a4f8 A64: Partially implement FCVTZU (scalar, fixed-point) and FCVTZS (scalar, fixed-point) 7479684 A64: Implement system register TPIDR_EL0 0fd75fd A64: Implement system registers FPCR and FPSR 31e370c A64: Implement system register CNTPCT_EL0 9a88fd3 A64: Implement system register CTR_EL0 1d16896 A64: Implement NEG (vector) 3184edf IR: Add IR instruction ZeroVector 31f8fbc emit_x64_floating_point: Add maybe_unused to preprocess parameter 567eb1a A64: Implement FMINNM (scalar) c6d8fa1 A64: Implement FMAXNM (scalar) 616056d constant_pool: Add frame parameter a3747cb A64: Implement ADDP (scalar) 5cd5d9f reg_alloc: Only exchange GPRs dd0452a A64: Implement DUP (element), scalar variant e5732ea emit_x64_floating_point: Correct FP{Max,Min}{32,64} implementations for -0/+0 40eb9c3 A64: Implement FMAX (scalar), FMIN (scalar) 7cef39b fuzz_with_unicorn: QEMU's implementation of FCVT is incorrect 826dce2 travis: Switch unicorn repository 9605f28 a64/config: Allow NaN emulation accuracy to be set e9435bc a64_emit_x64: Add conf to A64EmitContext 30b596d fuzz_with_unicorn: Explicitly test floating point instructions be292a8 A64: Implement FSQRT (scalar) 3c42d48 backend_x64: Accurately handle NaNs 4aefed0 fuzz_with_unicorn: Print AArch64 disassembly
* updated dynarmicFernandoS272018-02-171-0/+0
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* arm_dynarmic: Support direct page table accessMerryMage2018-02-121-0/+0
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* dynarmic: Fix bug due to Windows ABI mismatchMerryMage2018-02-091-0/+0
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* dynarmic: Update to 41ae12263MerryMage2018-02-091-0/+0
| | | | Changes: Primarily implementing more A64 instructions
* externals: Update dynarmicMerryMage2018-01-211-0/+0
| | | | | | | | | | | | | | | | | | | | | | | a6d17e A64: Implement AND (vector) 963453 tests/A64: Randomize vectors adcd34 tests/A64/unicorn: Print interrupt number when InterruptHook is hit 304c91 tests/A64: Allow RunTestInstance to start from an arbitrary offset d333b5 A64: Implement ADD (vector, vector) 1cf87a A64: Implement REV, REV32, and REV16 (#126) 9fc157 IR: Simplify types. F32 -> U32, F64 -> U64, F128 -> U128 50c181 reg_alloc: GetBitWidth: Add UNREACHABLE adccbf reg_alloc: Consider bitwidth of data and registers when emitting instructions 7b7f23 A64: Implement CSEL 2f8413 IR: Implement Conditional Select ebb3e8 A64/tests: Split unicorn sanity checking from other tests 5740a0 tests/A64: Single random instruction: Test branch instructions as well 0892b4 A64/translate/branch: bug: Read-after-write error in BLR e77bc2 A64: Implement SBFM, BFM, UBFM 0c37ca A64: Implement MOVN, MOVZ, MOVK b6bb59 travis: Print current test information e77207 fuzz_thumb: Off by one error a04ca2 ir/location_descriptor: Add missing <functional> header for std::hash 1e0f5c travis: Run A64 tests
* Update dynarmic to bc73004MerryMage2018-01-131-0/+0
| | | | | | | | | | | | | | | | | | bc73004 a64_merge_interpret_blocks: Remove debug output 4e656ed tests/A64: Randomize PSTATE.<NZCV> fd9530b A64: Optimization: Merge interpret blocks 3c9eb04 testenv: Use format constants 324f3fc tests/A64: Unicorn interface fixes 98ecbe7 tests/A64: Fuzz against unicorn b1d38e7 tests/A64: Move TestEnvironment to own header 5218ad9 A64/data_processing_pcrel: bug: ADR{,P} instructions sign extend their immediate b1a8c39 A64/data_processing_addsub: bug: {ADD,SUB}S (extended register) instructions write to ZR when d = 31 64827fb a64_emit_x64: bug: A64CallSupervisor trampled callee-save registers 1bfa04d emit_x64: bug: OP m/r64, imm32 form instructions sign-extend their immediate on x64 edadeea A64 inferface: Use two argument static_assert 9ab1304 A64: Add ExceptionRaised IR instruction 6843eed Update readme 7438d07 A64/translate: Add TranslateSingleInstruction function
* dynarmic: Update to 83afe435MerryMage2018-01-121-0/+0
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* arm_dynarmic: Implement coreMerryMage2018-01-121-0/+0
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* externals: Point dynarmic at a real commit.bunnei2018-01-041-0/+0
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* externals: Update dynarmic and xbyak.bunnei2017-10-251-0/+0
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* Merge remote-tracking branch 'upstream/master' into nxbunnei2017-10-101-0/+0
| | | | | | | | | | | | | | | | | # Conflicts: # src/core/CMakeLists.txt # src/core/arm/dynarmic/arm_dynarmic.cpp # src/core/arm/dyncom/arm_dyncom.cpp # src/core/hle/kernel/process.cpp # src/core/hle/kernel/thread.cpp # src/core/hle/kernel/thread.h # src/core/hle/kernel/vm_manager.cpp # src/core/loader/3dsx.cpp # src/core/loader/elf.cpp # src/core/loader/ncch.cpp # src/core/memory.cpp # src/core/memory.h # src/core/memory_setup.h
* Stop using reserved operator names (and/or/xor) with XbyakYuri Kunde Schlesner2017-06-171-0/+0
| | | | Also has the Dynarmic upgrade with the same change
* Update dynarmicYuri Kunde Schlesner2017-05-271-0/+0
| | | | | Updated to incorporate fix from MerryMage/dynarmic#106 which is required for using fmt in Citra.
* dynarmic: Update the submodule.Emmanuel Gil Peyrot2017-02-181-0/+0
| | | | | | This fixes a build issue on gcc 6 due to -Werror and a warning caused by boost::optional, see: https://github.com/MerryMage/dynarmic/issues/83
* arm_dynarmic: Update memory interfaceMerryMage2017-02-031-0/+0
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* arm_dynarmic: CP15 supportMerryMage2017-02-031-0/+0
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* arm_dynarmic: Provide MemoryReadCode callbackMerryMage2016-12-221-0/+0
| | | | Change of interface in dynarmic 36082087ded632079b16d24137fdd0c450ce82ea
* externals: Update DynarmicYuri Kunde Schlesner2016-12-151-0/+0
| | | | Required to be able to use Xbyak in Citra without header conflicts.
* Dynarmic: Update dynarmic to versionSubv2016-12-051-0/+0
| | | | | | | | | | | | | | | | | | | | | | | 54d051977f7a6af9c7596ba6a4e6eb467bd1e0bc dynarmic log: 54d0519 emit_x64: Use movdqa instead of movaps in EmitPackedSubU8 52e1445 Implement USUB8:33 2016 +0000 5c1aab1 Implement CLZ 1a1646d Implement UADD8 7cad694 IR: Implement new pseudo-operation GetGEFromOp 370f654 fuzz_arm: Add tests for parallel add/subtract (modulo) 25f21b5 emit_x64: Inline nzcv computation into EmitFPCompare32 and EmitFPCompare64 52fdec5 CMakeLists: Add support for LLVM on Windows cede5e4 emit_x64: Use xorps/xorpd when argument to TransferToFP32/TransferToFP64 is an immediate zero e166965 Implement VCMP2:33 2016 +0000 f2fe376 Support 64-bit immediates ff00b8c Document register allocator and return stack buffer optimization 95f34c6 reg_alloc: Remove unnecessary breaks after returns (#54) dc9707e externals: Update xbyak to 5.32 de1f831 microinstruction: Make use_count private (#53) 3621a92 reg_alloc: Register allocator related constraints belong with the rest of the register allocator
* dynarmic: Fix ABI violationMerryMage2016-11-301-0/+0
| | | | | | | Caused by not saving/restoring the x64 r15 register on entry/exit from JITted code. Closes #2224.
* Update dynarmic to the latest version (#2234)James Rowe2016-11-301-0/+0
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* dynarmic: Add new submodule.bunnei2016-09-151-0/+0
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