2 files changed, 75 insertions, 3 deletions

diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 4fdea0fdc..4d9745e48 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -153,7 +153,8 @@ void Maxwell3D::ProcessQueryGet() {
         break;
     }
     default:
-        UNIMPLEMENTED_MSG("Query mode %u not implemented", regs.query.query_get.mode.Value());
+        UNIMPLEMENTED_MSG("Query mode %u not implemented",
+                          static_cast<u32>(regs.query.query_get.mode.Value()));
     }
 }
 
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 096679162..aab282b77 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -31,8 +31,10 @@ public:
     struct Regs {
         static constexpr size_t NUM_REGS = 0xE36;
 
+        static constexpr size_t NumRenderTargets = 8;
         static constexpr size_t NumCBData = 16;
         static constexpr size_t NumVertexArrays = 32;
+        static constexpr size_t NumVertexAttributes = 32;
         static constexpr size_t MaxShaderProgram = 6;
         static constexpr size_t MaxShaderStage = 5;
         // Maximum number of const buffers per shader stage.
@@ -62,7 +64,68 @@ public:
 
         union {
             struct {
-                INSERT_PADDING_WORDS(0x557);
+                INSERT_PADDING_WORDS(0x200);
+
+                struct {
+                    u32 address_high;
+                    u32 address_low;
+                    u32 horiz;
+                    u32 vert;
+                    u32 format;
+                    u32 block_dimensions;
+                    u32 array_mode;
+                    u32 layer_stride;
+                    u32 base_layer;
+                    INSERT_PADDING_WORDS(7);
+
+                    GPUVAddr Address() const {
+                        return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
+                                                     address_low);
+                    }
+                } rt[NumRenderTargets];
+
+                INSERT_PADDING_WORDS(0xDD);
+
+                struct {
+                    u32 first;
+                    u32 count;
+                } vertex_buffer;
+
+                INSERT_PADDING_WORDS(0x99);
+
+                struct {
+                    u32 address_high;
+                    u32 address_low;
+                    u32 format;
+                    u32 block_dimensions;
+                    u32 layer_stride;
+
+                    GPUVAddr Address() const {
+                        return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) |
+                                                     address_low);
+                    }
+                } zeta;
+
+                INSERT_PADDING_WORDS(0x5B);
+
+                union {
+                    BitField<0, 5, u32> buffer;
+                    BitField<6, 1, u32> constant;
+                    BitField<7, 14, u32> offset;
+                    BitField<21, 6, u32> size;
+                    BitField<27, 3, u32> type;
+                    BitField<31, 1, u32> bgra;
+                } vertex_attrib_format[NumVertexAttributes];
+
+                INSERT_PADDING_WORDS(0xF);
+
+                struct {
+                    union {
+                        BitField<0, 4, u32> count;
+                    };
+                } rt_control;
+
+                INSERT_PADDING_WORDS(0xCF);
 
                 struct {
                     u32 tsc_address_high;
@@ -102,7 +165,10 @@ public:
                 INSERT_PADDING_WORDS(1);
                 struct {
                     u32 vertex_end_gl;
-                    u32 vertex_begin_gl;
+                    union {
+                        u32 vertex_begin_gl;
+                        BitField<0, 16, u32> topology;
+                    };
                 } draw;
                 INSERT_PADDING_WORDS(0x139);
                 struct {
@@ -291,6 +357,11 @@ private:
     static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4,                           \
                   "Field " #field_name " has invalid position")
 
+ASSERT_REG_POSITION(rt, 0x200);
+ASSERT_REG_POSITION(vertex_buffer, 0x35D);
+ASSERT_REG_POSITION(zeta, 0x3F8);
+ASSERT_REG_POSITION(vertex_attrib_format[0], 0x458);
+ASSERT_REG_POSITION(rt_control, 0x487);
 ASSERT_REG_POSITION(tsc, 0x557);
 ASSERT_REG_POSITION(tic, 0x55D);
 ASSERT_REG_POSITION(code_address, 0x582);