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-rw-r--r--src/video_core/engines/engine_interface.h22
-rw-r--r--src/video_core/engines/fermi_2d.cpp10
-rw-r--r--src/video_core/engines/fermi_2d.h8
-rw-r--r--src/video_core/engines/kepler_compute.cpp13
-rw-r--r--src/video_core/engines/kepler_compute.h8
-rw-r--r--src/video_core/engines/kepler_memory.cpp13
-rw-r--r--src/video_core/engines/kepler_memory.h8
-rw-r--r--src/video_core/engines/maxwell_3d.cpp38
-rw-r--r--src/video_core/engines/maxwell_3d.h36
-rw-r--r--src/video_core/engines/maxwell_dma.cpp50
-rw-r--r--src/video_core/engines/maxwell_dma.h8
-rw-r--r--src/video_core/engines/shader_bytecode.h4
12 files changed, 160 insertions, 58 deletions
diff --git a/src/video_core/engines/engine_interface.h b/src/video_core/engines/engine_interface.h
new file mode 100644
index 000000000..18a9db7e6
--- /dev/null
+++ b/src/video_core/engines/engine_interface.h
@@ -0,0 +1,22 @@
+// Copyright 2020 yuzu Emulator Project
+// Licensed under GPLv2 or any later version
+// Refer to the license.txt file included.
+
+#pragma once
+
+#include <type_traits>
+#include "common/common_types.h"
+
+namespace Tegra::Engines {
+
+class EngineInterface {
+public:
+ /// Write the value to the register identified by method.
+ virtual void CallMethod(u32 method, u32 method_argument, bool is_last_call) = 0;
+
+ /// Write multiple values to the register identified by method.
+ virtual void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
+ u32 methods_pending) = 0;
+};
+
+} // namespace Tegra::Engines
diff --git a/src/video_core/engines/fermi_2d.cpp b/src/video_core/engines/fermi_2d.cpp
index 8a47614d2..ff10ff40d 100644
--- a/src/video_core/engines/fermi_2d.cpp
+++ b/src/video_core/engines/fermi_2d.cpp
@@ -12,13 +12,13 @@ namespace Tegra::Engines {
Fermi2D::Fermi2D(VideoCore::RasterizerInterface& rasterizer) : rasterizer{rasterizer} {}
-void Fermi2D::CallMethod(const GPU::MethodCall& method_call) {
- ASSERT_MSG(method_call.method < Regs::NUM_REGS,
+void Fermi2D::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
+ ASSERT_MSG(method < Regs::NUM_REGS,
"Invalid Fermi2D register, increase the size of the Regs structure");
- regs.reg_array[method_call.method] = method_call.argument;
+ regs.reg_array[method] = method_argument;
- switch (method_call.method) {
+ switch (method) {
// Trigger the surface copy on the last register write. This is blit_src_y, but this is 64-bit,
// so trigger on the second 32-bit write.
case FERMI2D_REG_INDEX(blit_src_y) + 1: {
@@ -30,7 +30,7 @@ void Fermi2D::CallMethod(const GPU::MethodCall& method_call) {
void Fermi2D::CallMultiMethod(u32 method, const u32* base_start, u32 amount, u32 methods_pending) {
for (std::size_t i = 0; i < amount; i++) {
- CallMethod({method, base_start[i], 0, methods_pending - static_cast<u32>(i)});
+ CallMethod(method, base_start[i], methods_pending - static_cast<u32>(i) <= 1);
}
}
diff --git a/src/video_core/engines/fermi_2d.h b/src/video_core/engines/fermi_2d.h
index 939a5966d..8f37d053f 100644
--- a/src/video_core/engines/fermi_2d.h
+++ b/src/video_core/engines/fermi_2d.h
@@ -10,6 +10,7 @@
#include "common/common_funcs.h"
#include "common/common_types.h"
#include "common/math_util.h"
+#include "video_core/engines/engine_interface.h"
#include "video_core/gpu.h"
namespace Tegra {
@@ -31,16 +32,17 @@ namespace Tegra::Engines {
#define FERMI2D_REG_INDEX(field_name) \
(offsetof(Tegra::Engines::Fermi2D::Regs, field_name) / sizeof(u32))
-class Fermi2D final {
+class Fermi2D final : public EngineInterface {
public:
explicit Fermi2D(VideoCore::RasterizerInterface& rasterizer);
~Fermi2D() = default;
/// Write the value to the register identified by method.
- void CallMethod(const GPU::MethodCall& method_call);
+ void CallMethod(u32 method, u32 method_argument, bool is_last_call) override;
/// Write multiple values to the register identified by method.
- void CallMultiMethod(u32 method, const u32* base_start, u32 amount, u32 methods_pending);
+ void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
+ u32 methods_pending) override;
enum class Origin : u32 {
Center = 0,
diff --git a/src/video_core/engines/kepler_compute.cpp b/src/video_core/engines/kepler_compute.cpp
index 00a12175f..f6237fc6a 100644
--- a/src/video_core/engines/kepler_compute.cpp
+++ b/src/video_core/engines/kepler_compute.cpp
@@ -24,20 +24,19 @@ KeplerCompute::KeplerCompute(Core::System& system, VideoCore::RasterizerInterfac
KeplerCompute::~KeplerCompute() = default;
-void KeplerCompute::CallMethod(const GPU::MethodCall& method_call) {
- ASSERT_MSG(method_call.method < Regs::NUM_REGS,
+void KeplerCompute::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
+ ASSERT_MSG(method < Regs::NUM_REGS,
"Invalid KeplerCompute register, increase the size of the Regs structure");
- regs.reg_array[method_call.method] = method_call.argument;
+ regs.reg_array[method] = method_argument;
- switch (method_call.method) {
+ switch (method) {
case KEPLER_COMPUTE_REG_INDEX(exec_upload): {
upload_state.ProcessExec(regs.exec_upload.linear != 0);
break;
}
case KEPLER_COMPUTE_REG_INDEX(data_upload): {
- const bool is_last_call = method_call.IsLastCall();
- upload_state.ProcessData(method_call.argument, is_last_call);
+ upload_state.ProcessData(method_argument, is_last_call);
if (is_last_call) {
system.GPU().Maxwell3D().OnMemoryWrite();
}
@@ -54,7 +53,7 @@ void KeplerCompute::CallMethod(const GPU::MethodCall& method_call) {
void KeplerCompute::CallMultiMethod(u32 method, const u32* base_start, u32 amount,
u32 methods_pending) {
for (std::size_t i = 0; i < amount; i++) {
- CallMethod({method, base_start[i], 0, methods_pending - static_cast<u32>(i)});
+ CallMethod(method, base_start[i], methods_pending - static_cast<u32>(i) <= 1);
}
}
diff --git a/src/video_core/engines/kepler_compute.h b/src/video_core/engines/kepler_compute.h
index fe55fdfd0..18ceedfaf 100644
--- a/src/video_core/engines/kepler_compute.h
+++ b/src/video_core/engines/kepler_compute.h
@@ -11,6 +11,7 @@
#include "common/common_funcs.h"
#include "common/common_types.h"
#include "video_core/engines/const_buffer_engine_interface.h"
+#include "video_core/engines/engine_interface.h"
#include "video_core/engines/engine_upload.h"
#include "video_core/engines/shader_type.h"
#include "video_core/gpu.h"
@@ -39,7 +40,7 @@ namespace Tegra::Engines {
#define KEPLER_COMPUTE_REG_INDEX(field_name) \
(offsetof(Tegra::Engines::KeplerCompute::Regs, field_name) / sizeof(u32))
-class KeplerCompute final : public ConstBufferEngineInterface {
+class KeplerCompute final : public ConstBufferEngineInterface, public EngineInterface {
public:
explicit KeplerCompute(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
MemoryManager& memory_manager);
@@ -200,10 +201,11 @@ public:
"KeplerCompute LaunchParams has wrong size");
/// Write the value to the register identified by method.
- void CallMethod(const GPU::MethodCall& method_call);
+ void CallMethod(u32 method, u32 method_argument, bool is_last_call) override;
/// Write multiple values to the register identified by method.
- void CallMultiMethod(u32 method, const u32* base_start, u32 amount, u32 methods_pending);
+ void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
+ u32 methods_pending) override;
Texture::FullTextureInfo GetTexture(std::size_t offset) const;
diff --git a/src/video_core/engines/kepler_memory.cpp b/src/video_core/engines/kepler_memory.cpp
index 586ff15dc..dc71b2eec 100644
--- a/src/video_core/engines/kepler_memory.cpp
+++ b/src/video_core/engines/kepler_memory.cpp
@@ -19,20 +19,19 @@ KeplerMemory::KeplerMemory(Core::System& system, MemoryManager& memory_manager)
KeplerMemory::~KeplerMemory() = default;
-void KeplerMemory::CallMethod(const GPU::MethodCall& method_call) {
- ASSERT_MSG(method_call.method < Regs::NUM_REGS,
+void KeplerMemory::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
+ ASSERT_MSG(method < Regs::NUM_REGS,
"Invalid KeplerMemory register, increase the size of the Regs structure");
- regs.reg_array[method_call.method] = method_call.argument;
+ regs.reg_array[method] = method_argument;
- switch (method_call.method) {
+ switch (method) {
case KEPLERMEMORY_REG_INDEX(exec): {
upload_state.ProcessExec(regs.exec.linear != 0);
break;
}
case KEPLERMEMORY_REG_INDEX(data): {
- const bool is_last_call = method_call.IsLastCall();
- upload_state.ProcessData(method_call.argument, is_last_call);
+ upload_state.ProcessData(method_argument, is_last_call);
if (is_last_call) {
system.GPU().Maxwell3D().OnMemoryWrite();
}
@@ -44,7 +43,7 @@ void KeplerMemory::CallMethod(const GPU::MethodCall& method_call) {
void KeplerMemory::CallMultiMethod(u32 method, const u32* base_start, u32 amount,
u32 methods_pending) {
for (std::size_t i = 0; i < amount; i++) {
- CallMethod({method, base_start[i], 0, methods_pending - static_cast<u32>(i)});
+ CallMethod(method, base_start[i], methods_pending - static_cast<u32>(i) <= 1);
}
}
diff --git a/src/video_core/engines/kepler_memory.h b/src/video_core/engines/kepler_memory.h
index bb26fb030..5b7f71a00 100644
--- a/src/video_core/engines/kepler_memory.h
+++ b/src/video_core/engines/kepler_memory.h
@@ -10,6 +10,7 @@
#include "common/bit_field.h"
#include "common/common_funcs.h"
#include "common/common_types.h"
+#include "video_core/engines/engine_interface.h"
#include "video_core/engines/engine_upload.h"
#include "video_core/gpu.h"
@@ -32,16 +33,17 @@ namespace Tegra::Engines {
#define KEPLERMEMORY_REG_INDEX(field_name) \
(offsetof(Tegra::Engines::KeplerMemory::Regs, field_name) / sizeof(u32))
-class KeplerMemory final {
+class KeplerMemory final : public EngineInterface {
public:
KeplerMemory(Core::System& system, MemoryManager& memory_manager);
~KeplerMemory();
/// Write the value to the register identified by method.
- void CallMethod(const GPU::MethodCall& method_call);
+ void CallMethod(u32 method, u32 method_argument, bool is_last_call) override;
/// Write multiple values to the register identified by method.
- void CallMultiMethod(u32 method, const u32* base_start, u32 amount, u32 methods_pending);
+ void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
+ u32 methods_pending) override;
struct Regs {
static constexpr size_t NUM_REGS = 0x7F;
diff --git a/src/video_core/engines/maxwell_3d.cpp b/src/video_core/engines/maxwell_3d.cpp
index 39e3b66a2..024c9e43b 100644
--- a/src/video_core/engines/maxwell_3d.cpp
+++ b/src/video_core/engines/maxwell_3d.cpp
@@ -44,6 +44,12 @@ void Maxwell3D::InitializeRegisterDefaults() {
viewport.depth_range_near = 0.0f;
viewport.depth_range_far = 1.0f;
}
+ for (auto& viewport : regs.viewport_transform) {
+ viewport.swizzle.x.Assign(Regs::ViewportSwizzle::PositiveX);
+ viewport.swizzle.y.Assign(Regs::ViewportSwizzle::PositiveY);
+ viewport.swizzle.z.Assign(Regs::ViewportSwizzle::PositiveZ);
+ viewport.swizzle.w.Assign(Regs::ViewportSwizzle::PositiveW);
+ }
// Doom and Bomberman seems to use the uninitialized registers and just enable blend
// so initialize blend registers with sane values
@@ -125,12 +131,10 @@ void Maxwell3D::CallMacroMethod(u32 method, std::size_t num_parameters, const u3
}
}
-void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
- const u32 method = method_call.method;
-
+void Maxwell3D::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
if (method == cb_data_state.current) {
- regs.reg_array[method] = method_call.argument;
- ProcessCBData(method_call.argument);
+ regs.reg_array[method] = method_argument;
+ ProcessCBData(method_argument);
return;
} else if (cb_data_state.current != null_cb_data) {
FinishCBData();
@@ -153,10 +157,10 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
executing_macro = method;
}
- macro_params.push_back(method_call.argument);
+ macro_params.push_back(method_argument);
// Call the macro when there are no more parameters in the command buffer
- if (method_call.IsLastCall()) {
+ if (is_last_call) {
CallMacroMethod(executing_macro, macro_params.size(), macro_params.data());
macro_params.clear();
}
@@ -166,7 +170,7 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
ASSERT_MSG(method < Regs::NUM_REGS,
"Invalid Maxwell3D register, increase the size of the Regs structure");
- u32 arg = method_call.argument;
+ u32 arg = method_argument;
// Keep track of the register value in shadow_state when requested.
if (shadow_state.shadow_ram_control == Regs::ShadowRamControl::Track ||
shadow_state.shadow_ram_control == Regs::ShadowRamControl::TrackWithFilter) {
@@ -184,8 +188,12 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
}
switch (method) {
+ case MAXWELL3D_REG_INDEX(wait_for_idle): {
+ rasterizer.WaitForIdle();
+ break;
+ }
case MAXWELL3D_REG_INDEX(shadow_ram_control): {
- shadow_state.shadow_ram_control = static_cast<Regs::ShadowRamControl>(method_call.argument);
+ shadow_state.shadow_ram_control = static_cast<Regs::ShadowRamControl>(method_argument);
break;
}
case MAXWELL3D_REG_INDEX(macros.data): {
@@ -268,7 +276,6 @@ void Maxwell3D::CallMethod(const GPU::MethodCall& method_call) {
break;
}
case MAXWELL3D_REG_INDEX(data_upload): {
- const bool is_last_call = method_call.IsLastCall();
upload_state.ProcessData(arg, is_last_call);
if (is_last_call) {
OnMemoryWrite();
@@ -326,7 +333,7 @@ void Maxwell3D::CallMultiMethod(u32 method, const u32* base_start, u32 amount,
}
default: {
for (std::size_t i = 0; i < amount; i++) {
- CallMethod({method, base_start[i], 0, methods_pending - static_cast<u32>(i)});
+ CallMethod(method, base_start[i], methods_pending - static_cast<u32>(i) <= 1);
}
}
}
@@ -356,16 +363,15 @@ void Maxwell3D::StepInstance(const MMEDrawMode expected_mode, const u32 count) {
StepInstance(expected_mode, count);
}
-void Maxwell3D::CallMethodFromMME(const GPU::MethodCall& method_call) {
- const u32 method = method_call.method;
+void Maxwell3D::CallMethodFromMME(u32 method, u32 method_argument) {
if (mme_inline[method]) {
- regs.reg_array[method] = method_call.argument;
+ regs.reg_array[method] = method_argument;
if (method == MAXWELL3D_REG_INDEX(vertex_buffer.count) ||
method == MAXWELL3D_REG_INDEX(index_array.count)) {
const MMEDrawMode expected_mode = method == MAXWELL3D_REG_INDEX(vertex_buffer.count)
? MMEDrawMode::Array
: MMEDrawMode::Indexed;
- StepInstance(expected_mode, method_call.argument);
+ StepInstance(expected_mode, method_argument);
} else if (method == MAXWELL3D_REG_INDEX(draw.vertex_begin_gl)) {
mme_draw.instance_mode =
(regs.draw.instance_next != 0) || (regs.draw.instance_cont != 0);
@@ -377,7 +383,7 @@ void Maxwell3D::CallMethodFromMME(const GPU::MethodCall& method_call) {
if (mme_draw.current_mode != MMEDrawMode::Undefined) {
FlushMMEInlineDraw();
}
- CallMethod(method_call);
+ CallMethod(method, method_argument, true);
}
}
diff --git a/src/video_core/engines/maxwell_3d.h b/src/video_core/engines/maxwell_3d.h
index 3dfba8197..05dd6b39b 100644
--- a/src/video_core/engines/maxwell_3d.h
+++ b/src/video_core/engines/maxwell_3d.h
@@ -19,6 +19,7 @@
#include "common/math_util.h"
#include "video_core/engines/const_buffer_engine_interface.h"
#include "video_core/engines/const_buffer_info.h"
+#include "video_core/engines/engine_interface.h"
#include "video_core/engines/engine_upload.h"
#include "video_core/engines/shader_type.h"
#include "video_core/gpu.h"
@@ -48,7 +49,7 @@ namespace Tegra::Engines {
#define MAXWELL3D_REG_INDEX(field_name) \
(offsetof(Tegra::Engines::Maxwell3D::Regs, field_name) / sizeof(u32))
-class Maxwell3D final : public ConstBufferEngineInterface {
+class Maxwell3D final : public ConstBufferEngineInterface, public EngineInterface {
public:
explicit Maxwell3D(Core::System& system, VideoCore::RasterizerInterface& rasterizer,
MemoryManager& memory_manager);
@@ -575,6 +576,17 @@ public:
Replay = 3,
};
+ enum class ViewportSwizzle : u32 {
+ PositiveX = 0,
+ NegativeX = 1,
+ PositiveY = 2,
+ NegativeY = 3,
+ PositiveZ = 4,
+ NegativeZ = 5,
+ PositiveW = 6,
+ NegativeW = 7,
+ };
+
struct RenderTargetConfig {
u32 address_high;
u32 address_low;
@@ -618,7 +630,14 @@ public:
f32 translate_x;
f32 translate_y;
f32 translate_z;
- INSERT_UNION_PADDING_WORDS(2);
+ union {
+ u32 raw;
+ BitField<0, 3, ViewportSwizzle> x;
+ BitField<4, 3, ViewportSwizzle> y;
+ BitField<8, 3, ViewportSwizzle> z;
+ BitField<12, 3, ViewportSwizzle> w;
+ } swizzle;
+ INSERT_UNION_PADDING_WORDS(1);
Common::Rectangle<f32> GetRect() const {
return {
@@ -709,7 +728,9 @@ public:
union {
struct {
- INSERT_UNION_PADDING_WORDS(0x45);
+ INSERT_UNION_PADDING_WORDS(0x44);
+
+ u32 wait_for_idle;
struct {
u32 upload_address;
@@ -1179,6 +1200,7 @@ public:
BitField<0, 1, u32> depth_range_0_1;
BitField<3, 1, u32> depth_clamp_near;
BitField<4, 1, u32> depth_clamp_far;
+ BitField<11, 1, u32> depth_clamp_disabled;
} view_volume_clip_control;
INSERT_UNION_PADDING_WORDS(0x1F);
@@ -1357,13 +1379,14 @@ public:
u32 GetRegisterValue(u32 method) const;
/// Write the value to the register identified by method.
- void CallMethod(const GPU::MethodCall& method_call);
+ void CallMethod(u32 method, u32 method_argument, bool is_last_call) override;
/// Write multiple values to the register identified by method.
- void CallMultiMethod(u32 method, const u32* base_start, u32 amount, u32 methods_pending);
+ void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
+ u32 methods_pending) override;
/// Write the value to the register identified by method.
- void CallMethodFromMME(const GPU::MethodCall& method_call);
+ void CallMethodFromMME(u32 method, u32 method_argument);
void FlushMMEInlineDraw();
@@ -1535,6 +1558,7 @@ private:
static_assert(offsetof(Maxwell3D::Regs, field_name) == position * 4, \
"Field " #field_name " has invalid position")
+ASSERT_REG_POSITION(wait_for_idle, 0x44);
ASSERT_REG_POSITION(macros, 0x45);
ASSERT_REG_POSITION(shadow_ram_control, 0x49);
ASSERT_REG_POSITION(upload, 0x60);
diff --git a/src/video_core/engines/maxwell_dma.cpp b/src/video_core/engines/maxwell_dma.cpp
index 6630005b0..01d7df405 100644
--- a/src/video_core/engines/maxwell_dma.cpp
+++ b/src/video_core/engines/maxwell_dma.cpp
@@ -17,16 +17,16 @@ namespace Tegra::Engines {
MaxwellDMA::MaxwellDMA(Core::System& system, MemoryManager& memory_manager)
: system{system}, memory_manager{memory_manager} {}
-void MaxwellDMA::CallMethod(const GPU::MethodCall& method_call) {
- ASSERT_MSG(method_call.method < Regs::NUM_REGS,
+void MaxwellDMA::CallMethod(u32 method, u32 method_argument, bool is_last_call) {
+ ASSERT_MSG(method < Regs::NUM_REGS,
"Invalid MaxwellDMA register, increase the size of the Regs structure");
- regs.reg_array[method_call.method] = method_call.argument;
+ regs.reg_array[method] = method_argument;
#define MAXWELLDMA_REG_INDEX(field_name) \
(offsetof(Tegra::Engines::MaxwellDMA::Regs, field_name) / sizeof(u32))
- switch (method_call.method) {
+ switch (method) {
case MAXWELLDMA_REG_INDEX(exec): {
HandleCopy();
break;
@@ -39,7 +39,7 @@ void MaxwellDMA::CallMethod(const GPU::MethodCall& method_call) {
void MaxwellDMA::CallMultiMethod(u32 method, const u32* base_start, u32 amount,
u32 methods_pending) {
for (std::size_t i = 0; i < amount; i++) {
- CallMethod({method, base_start[i], 0, methods_pending - static_cast<u32>(i)});
+ CallMethod(method, base_start[i], methods_pending - static_cast<u32>(i) <= 1);
}
}
@@ -90,7 +90,47 @@ void MaxwellDMA::HandleCopy() {
ASSERT(regs.exec.enable_2d == 1);
if (regs.exec.is_dst_linear && !regs.exec.is_src_linear) {
+
ASSERT(regs.src_params.BlockDepth() == 0);
+ // Optimized path for micro copies.
+ if (regs.dst_pitch * regs.y_count < Texture::GetGOBSize() && regs.dst_pitch <= 64) {
+ const u32 bytes_per_pixel = regs.dst_pitch / regs.x_count;
+ const std::size_t src_size = Texture::GetGOBSize();
+ const std::size_t dst_size = regs.dst_pitch * regs.y_count;
+ u32 pos_x = regs.src_params.pos_x;
+ u32 pos_y = regs.src_params.pos_y;
+ const u64 offset =
+ Texture::GetGOBOffset(regs.src_params.size_x, regs.src_params.size_y, pos_x, pos_y,
+ regs.src_params.BlockDepth(), bytes_per_pixel);
+ const u32 x_in_gob = 64 / bytes_per_pixel;
+ pos_x = pos_x % x_in_gob;
+ pos_y = pos_y % 8;
+
+ if (read_buffer.size() < src_size) {
+ read_buffer.resize(src_size);
+ }
+
+ if (write_buffer.size() < dst_size) {
+ write_buffer.resize(dst_size);
+ }
+
+ if (Settings::IsGPULevelExtreme()) {
+ memory_manager.ReadBlock(source + offset, read_buffer.data(), src_size);
+ memory_manager.ReadBlock(dest, write_buffer.data(), dst_size);
+ } else {
+ memory_manager.ReadBlockUnsafe(source + offset, read_buffer.data(), src_size);
+ memory_manager.ReadBlockUnsafe(dest, write_buffer.data(), dst_size);
+ }
+
+ Texture::UnswizzleSubrect(regs.x_count, regs.y_count, regs.dst_pitch,
+ regs.src_params.size_x, bytes_per_pixel, read_buffer.data(),
+ write_buffer.data(), regs.src_params.BlockHeight(), pos_x,
+ pos_y);
+
+ memory_manager.WriteBlock(dest, write_buffer.data(), dst_size);
+
+ return;
+ }
// If the input is tiled and the output is linear, deswizzle the input and copy it over.
const u32 bytes_per_pixel = regs.dst_pitch / regs.x_count;
const std::size_t src_size = Texture::CalculateSize(
diff --git a/src/video_core/engines/maxwell_dma.h b/src/video_core/engines/maxwell_dma.h
index c43ed8194..502dd8509 100644
--- a/src/video_core/engines/maxwell_dma.h
+++ b/src/video_core/engines/maxwell_dma.h
@@ -10,6 +10,7 @@
#include "common/bit_field.h"
#include "common/common_funcs.h"
#include "common/common_types.h"
+#include "video_core/engines/engine_interface.h"
#include "video_core/gpu.h"
namespace Core {
@@ -27,16 +28,17 @@ namespace Tegra::Engines {
* https://github.com/envytools/envytools/blob/master/rnndb/fifo/gk104_copy.xml
*/
-class MaxwellDMA final {
+class MaxwellDMA final : public EngineInterface {
public:
explicit MaxwellDMA(Core::System& system, MemoryManager& memory_manager);
~MaxwellDMA() = default;
/// Write the value to the register identified by method.
- void CallMethod(const GPU::MethodCall& method_call);
+ void CallMethod(u32 method, u32 method_argument, bool is_last_call) override;
/// Write multiple values to the register identified by method.
- void CallMultiMethod(u32 method, const u32* base_start, u32 amount, u32 methods_pending);
+ void CallMultiMethod(u32 method, const u32* base_start, u32 amount,
+ u32 methods_pending) override;
struct Regs {
static constexpr std::size_t NUM_REGS = 0x1D6;
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index cde3a26b9..8dae754d4 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -814,6 +814,10 @@ union Instruction {
} alu_integer;
union {
+ BitField<43, 1, u64> x;
+ } iadd;
+
+ union {
BitField<39, 1, u64> ftz;
BitField<32, 1, u64> saturate;
BitField<49, 2, HalfMerge> merge;
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-04 00:28:15 +0100