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-rw-r--r--src/video_core/engines/maxwell_dma.cpp6
-rw-r--r--src/video_core/engines/shader_bytecode.h4
2 files changed, 7 insertions, 3 deletions
diff --git a/src/video_core/engines/maxwell_dma.cpp b/src/video_core/engines/maxwell_dma.cpp
index 442138988..c298f0bfb 100644
--- a/src/video_core/engines/maxwell_dma.cpp
+++ b/src/video_core/engines/maxwell_dma.cpp
@@ -49,7 +49,11 @@ void MaxwellDMA::HandleCopy() {
ASSERT(regs.src_params.pos_y == 0);
ASSERT(regs.dst_params.pos_x == 0);
ASSERT(regs.dst_params.pos_y == 0);
- ASSERT(regs.exec.is_dst_linear != regs.exec.is_src_linear);
+
+ if (regs.exec.is_dst_linear == regs.exec.is_src_linear) {
+ Memory::CopyBlock(dest_cpu, source_cpu, regs.x_count * regs.y_count);
+ return;
+ }
u8* src_buffer = Memory::GetPointer(source_cpu);
u8* dst_buffer = Memory::GetPointer(dest_cpu);
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index cb4db0679..86fd64979 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -142,6 +142,7 @@ enum class PredCondition : u64 {
GreaterThan = 4,
NotEqual = 5,
GreaterEqual = 6,
+ NotEqualWithNan = 13,
// TODO(Subv): Other condition types
};
@@ -165,7 +166,6 @@ enum class SubOp : u64 {
Lg2 = 0x3,
Rcp = 0x4,
Rsq = 0x5,
- Min = 0x8,
};
enum class F2iRoundingOp : u64 {
@@ -209,7 +209,7 @@ union Instruction {
} pred;
BitField<19, 1, u64> negate_pred;
BitField<20, 8, Register> gpr20;
- BitField<20, 7, SubOp> sub_op;
+ BitField<20, 4, SubOp> sub_op;
BitField<28, 8, Register> gpr28;
BitField<39, 8, Register> gpr39;
BitField<48, 16, u64> opcode;