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-rw-r--r--src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp10
-rw-r--r--src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.h2
2 files changed, 8 insertions, 4 deletions
diff --git a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp
index d5558f29f..be6b88f98 100644
--- a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp
+++ b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.cpp
@@ -77,9 +77,13 @@ u32 nvhost_ctrl_gpu::GetCharacteristics(const std::vector<u8>& input, std::vecto
u32 nvhost_ctrl_gpu::GetTPCMasks(const std::vector<u8>& input, std::vector<u8>& output) {
IoctlGpuGetTpcMasksArgs params{};
std::memcpy(&params, input.data(), input.size());
- NGLOG_WARNING(Service_NVDRV, "(STUBBED) called, mask=0x{:X}, mask_buf_addr=0x{:X}",
- params.mask_buf_size, params.mask_buf_addr);
- params.unk = 0xcafe; // TODO(ogniK): Needs to be non 0, what does this actually do?
+ NGLOG_INFO(Service_NVDRV, "called, mask=0x{:X}, mask_buf_addr=0x{:X}", params.mask_buf_size,
+ params.mask_buf_addr);
+ // TODO(ogniK): Confirm value on hardware
+ if (params.mask_buf_size)
+ params.tpc_mask_size = 4 * 1; // 4 * num_gpc
+ else
+ params.tpc_mask_size = 0;
std::memcpy(output.data(), &params, sizeof(params));
return 0;
}
diff --git a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.h b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.h
index 31040cdbe..2d43598b1 100644
--- a/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.h
+++ b/src/core/hle/service/nvdrv/devices/nvhost_ctrl_gpu.h
@@ -86,7 +86,7 @@ private:
/// [in] pointer to TPC mask buffer. It will receive one 32-bit TPC mask per GPC or 0 if
/// GPC is not enabled or not present. This parameter is ignored if mask_buf_size is 0.
u64_le mask_buf_addr;
- u64_le unk; // Nintendo add this?
+ u64_le tpc_mask_size; // Nintendo add this?
};
static_assert(sizeof(IoctlGpuGetTpcMasksArgs) == 24,
"IoctlGpuGetTpcMasksArgs is incorrect size");